Wen-Teng Chang

External Stresses on Tensile and Compressive Contact Etching Stop Layer SOI MOSFETs

A n-/p-SOI MOSFET capped with a standard 380 Å tensile contact etching stop layer (CESL) and a 700 Å compressive CESL and with SOI thicknesses of 500/700/900 Å were measured in this paper. Additionally, external uniaxial compressive stresses with both longitudinal and transverse directions up to 45.7 MPa were applied on the devices sitting on cut silicon bars. Temperature-induced threshold voltage shifts and input-referred voltage noise showed bigger depletion zones and higher noise in the device with compressive CESL. The measurement suggests that both SOI thickness and CESL type are critical for mobility enhancement or degradation of devices. The capped compressive CESL for n-/p-SOI MOSFETs demonstrated higher piezoresistive coefficient compared with tensile CESL under external uniaxial compressive stresses for both longitudinal and transverse configurations.

Electrical Characterization of Microelectromechanical Silicon Carbide Resonators

This manuscript describes the findings of a study to investigate the performance of SiC MEMS resonators with respect to resonant frequency and quality factor under a variety of testing conditions, including various ambient pressures, AC drive voltages, bias potentials and temperatures. The sample set included both single-crystal and polycrystalline 3C-SiC lateral resonators. The experimental results show that operation at reduced pressures increases the resonant frequency as damping due to the gas-rarefaction effect becomes significant. Both DC bias and AC drive voltages result in nonlinearities, but the AC drive voltage is more sensitive to noise. The AC voltage has a voltage coefficient of 1∼4ppm/V at a DC bias of 40V. The coefficient of DC bias is about -11ppm/V to - 21ppm/V for poly-SiC, which is more than a factor of two better than a similarly designed polysilicon resonator (-54 ppm/V). The effective stiffness of the resonator decreases (softens) as the bias potential is increased, but increases (hardens) as drive voltage increase when scan is from low to high frequency. The resonant frequency decreases slightly with increasing temperature, exhibiting a temperature coefficient of -22 ppm/°C, between 22°C and 60°C. The thermal expansion mismatch between the SiC device and the Si substrate could be a reason that thermal coefficient for these SiC resonators is about twofold higher than similar polysilicon resonators. However, the Qs appear to exhibit no temperature dependence in this range.

Energy Dissipation in Folded-Beam MEMS Resonators Made from Single Crystal and Polycrystalline 3C-SiC Films

This paper examines energy dissipation in MEMS folded-beam resonators made from single crystal and polycrystalline 3C-SiC (poly-SiC) films. The single crystal films were grown at 1280degC by atmospheric pressure chemical vapor deposition (APCVD) while the polycrystalline films were deposited by low pressure chemical vapor deposition (LPCVD) at 900degC. Testing was conducted a pressure of 30 muTorr using a transimpedance amplifier-based circuit. Results show that the quality factor is five times higher for the single crystal SiC devices than the poly-SiC devices. Analysis of the principal components governing energy dissipation indicates that the difference is due to film micro structure and the associated internal losses.

Impact of Fin Width and Back Bias Under Hot Carrier Injection on Double-Gate FinFETs

This study compares the effects of n-channel double-gate FinFETs with fin widths (Wfin) of 10 and 25 nm with those of such devices with back biases and hot carrier injection (HCI). Compared with the device with a wide Wfin, the device with a narrow Wfin exhibits a larger current tuning range but a more off-state current leakage at a positive back bias because of the forward-biased p-n junction and the higher degradation under HCI. The gate-induced drain leakage significantly deteriorates with a positive back bias after HCI because of the generation of interfacial charges. However, a negative back bias causing hot hole injection during HCI can alleviate the degradation compared with unbiased and positive-biased devices.

Piezoresistive sensor of short- and long- channel MOSFETs on (100) silicon

This study evaluated metal oxide semiconductor field-effect transistor (MOSFETs) with channel lengths/widths of 0.135/10, 0.45/10, and 10/10 ¿m for both the n- and p- channel types used as sensing elements. The results show that the devices with channel lengths/widths of 0.45/10 and 10/10 ¿m have flat saturation current. It suggests that there is a requirement for a device to have a channel length of over 0.45 ¿m to provide better sensing characterization to normalized current change. The experimental result also demonstrates the fine linear dependence of stress distribution to the distance of tested devices from the clamping end for a silicon cantilever. The stress distribution is detected via normalized current change for all the three sizes of channel length and for both the n and p- types. Moreover, the device with larger channel length has better stress sensitivity than that with the smaller one, when the channel width is fixed at 10 ¿m.

Geometric Design of Microbolometers Made From CMOS Polycrystalline Silicon

In this paper, microbolometers with different geometric designs were fabricated using polycrystalline silicon (polysilicon) films from TSMC 0.35 μm (D35 type) and 0.18 μm (T18 type). D35 microbolometers with high-resistance films showed negative temperature coefficient of resistance (TCR) values, whereas T18 microbolometers with low-resistance films showed positive TCR values. Results indicate that conventional designs with large areas of infrared absorbers can be optimized using uniform suspended arms throughout the microbolometer in the two types of devices. Finite element modeling indicates that the heat flux of microbolometers with uniform beams is evenly distributed and thus results in improved TCR values.

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

Abstract This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

This paper measures the n- and p-MOSFETs fabricated through 65-nm high- k/metal gate CMOSFET process flow. The [110] channels of the Si cap on SiGe with different width (W) and length (L) ratios were compared with Si-only channels. The results show that a high W-L ratio in the [110] n-channel can alleviate the degradation of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel can improve the performance; however, the ratio should at least be below two in this paper. The dominance of the longitudinal or transverse configurations successfully explains this phenomenon because of the reliance of the different levels of piezoresistance coefficient on the channel orientation. The threshold voltage shifts versus the W-L ratio in the p-channel is in agreement with the result. The result is verified by a quantitative current comparison at a high bias in the n-/p-channels between the strained SiGe and Si-only channels, which shows that an extreme W-L ratio in the original biaxially strained SiGe channel can result in longitudinal or transverse strain, thereby leading to different levels of performance degradation/improvement.

Modeling of Feedthrough Capacitance for MEMS Folded-Beam Silicon Carbide Resonators

This manuscript analyzes the feedthrough capacitance of folded-beam MEMS-based silicon carbide (SiC) lateral resonators. Additionally, feedthrough capacitance for MEMS resonators via electrical measurement was estimated by matching simulated with measured Bode plots from a network analyzer. The feedthrough capacitance was 0.1-1 pF, as determined by Bode plots using feedthrough capacitance as a key input for the measured Bode plot.

CLAMPING LOSSES OF FOLDED- AND STRAIGHT-BEAM MEMS RESONATORS MADE FROM POLYCRYSTALLINE 3C-SiC FILMS

This paper presents an analysis of clamping losses in microelectromechanical systems (MEMS)-based, flexural mode silicon carbide (SiC) lateral resonators. The study includes folded- and straight-beam resonators made from (111) polycrystalline 3C-SiC side by side. The device testing was conducted at 30 µTorr using a transimpedanceamplifier-based circuit to measure the total quality factor. It was found that thermoelastic damping (TED) in SiC MEMS-based lateral resonators has minimal contributions to overall energy dissipation in the aforementioned devices. Moreover, the difference in material losses of these devices is negligible due to their similar microstructure. In this case, clamping losses are responsible when one is comparing the energy dissipation mechanism of these two types of resonators. The findings showed that the total losses for a folded-beam resonator were reduced by more than 10 times that for a straight-beam resonator when the beam lengths were set at 150 µm and operated at the same level of resonant frequency. The clamping coefficient of the folded-beam resonator was between 0.7 and 1.8, suggesting that the effective dimension of a folded-beam resonator should include part of the proof mass.