Po-Ying Chen

The Improvement of High-

The impact of the Si cap/SiGe layer on the Hf-based high-<i>k</i> /metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high-<i>k</i>/metal gate SiGe pMOSFET can be obtained with an appropriate <i>V</i>_TH (~0.3 V), low <i>C</i> -<i>V</i> hysteresis ( <; 5 mV), and better I_ON - I_OFF , <i>V</i>_TH rolloff, and <i>V</i>_TH stability. By the way, the related interface trap density in the high-<i>k</i> gate stack layer can also be reduced, thus improving the devices NBTI and HCI stressing-induced reliability.

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Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (θ) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

In this paper, the impact of strain engineering on device performance and reliability for fully silicide gate silicon-on-insulator CMOSFET was investigated. With characterizing devices electrical property after hot carrier (HC) and positive/negative bias instability voltage stressing, we found similar enhancement on device performance but different behavior on voltage-stressing-induced device degradation for n/pMOSFETs. Related noise analysis and charge pumping techniques were used to investigate the strain-induced oxide defect which will accelerate device degradation after long-time HC voltage stressing and/or bias instability voltage stressing.

Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths (WFin_bottom), which will impact the device performance and reliability. For n-type FinFETs, the experimental results show that the thinner WFin_bottom device performs better reliability under HCI stress due to higher inversion carrier density at the center of Si-fin channel. For p-type FinFETs under negative bias stressing, the thinner WFin_bottom device shows more serious degradation on drain current (ID) and subthreshold swing (SS) with the increasing of stressing voltage due to larger electric field within the Si-fin and higher energy of inversion holes, while the thicker WFin_bottom device shows almost insensitively degradation with the variation of stressing voltage.

The Impact of Strain Technology on FUSI Gate SOI CMOSFET

In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 106 A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Blacks power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET

We investigated the reliability of a board-level wafer-level chip-scale package (WLCSP) subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 degC. A reasonably good correlation between mean-time-to-failure of the WLCSP test vehicle and the average current density carried by a solder joint was obtained. Moreover, the trace breakage was identified as the mandatory failure mode under these current stressing conditions. In-situ observations were also conducted to further identify this particular failure mode

Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

We demonstrated a high-k/metal gate-last SiGe-SOI CMOSFET process with optimized strain technology for high performance concerns. The impact of SOI thickness and strain from Ge, CESL, and high-k material/metal-gate are inspected. An appropriate post treatment is proposed to improve quality of stack Hf-based dielectric. We achieved a high manufacturability 28nm SiGe-SOI channel Hf-based high-k/TiN-based metal-gate last CMOSFET with good VT roll-off, lower device leakage and better reliability.

An experimental investigation of current stressing on wafer-level chip-scale packages

The impact of strain induced oxide trap charge on the performance and reliability of contact etch stop SiN layer capped, fully silicided metal gate, fully depleted SOI (FDSOI) CMOSFET is investigated. For an ultra thin nitride oxide, the position of these oxide trap charge can be evaluated by variable frequency noise spectrum and variable frequency charge pumping technique. Gate oxide film bending caused by net stress from these strain technologies was considered as the main reason for bulk oxide trap charge formation. We find that a strained SOI MOSFET with a thinner SOI is more subjective to the stress than the thicker one, and the thinner SOI device possesses a higher oxide/Si interface trap charge density which will degrade the channel mobility. On the other hand, more bulk oxide trap, which existed in the strained device having a thicker SOI, was the dominate factor on current/voltage stress induced device degradation.

A proposed high manufacturability strain technology for high-k/metal gate SiGe-SOI CMOSFET

In this paper, the impact of fin number on device performance and hot carrier induced device degradation was investigated for n-channel tri-gate multi-fin FinFET with different fin numbers. The threshold voltage (VTH) shift, transconductance, and subthreshold swing degradation were extracted to determine the degradation of device. It was found that the device with fewer fins shows better device performance, but suffer from more serious hot carrier induced device degradation. It is suggested that the existed coupling effect between the fins reduces the equivalent electric field in the multi-fins devices, thus shows better reliability than the single-fin device does after hot carrier stress.

Impact of oxide trap charge on performance of strained fully depleted SOI metal-gate MOSFET

The effect of crystal-originated particles (COPs) on ultra-thin gate oxide for recent ultra large-scale integration (ULSI) devices were studied. Various Czochralski (CZ) silicon wafers were prepared by controlling the pulling speed of silicon ingots to determine the relationships between COPs and the breakdown characteristics of the ultra thin-gate oxide. The distribution of COPs, measured by optical shallow defect analysis and the use of a particle counter, was compared with the results of time-independent dielectric breakdown (TZDB), time-dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) for gate oxides with thicknesses of 2.5 -5 nm. The results reveal no appreciable oxide degradation below an oxide thickness of approximately 3 nm; above this threshold value, the defect density depends strongly on the presence of crystal-originated particles. The COPs are a major factor in the degradation of ultra-thin gate oxide (less than 5 nm) in ULSI devices.