Wenfeng Zhao

Neuronix enables continuous, simultaneous neural recording and electrical microstimulation

This paper reports a novel neurotechnology (Neuronix) and its validation through experiments. It is a miniature system-on-chip (SoC) that allows recording with simultaneous electrical microstimulation. This function has not been demonstrated before and enables precise, closed-loop neuromodulation. Neuronix represents recent advancement in brain technology and applies to both animal research and clinical applications.This paper reports a novel neurotechnology (Neuronix) and its validation through experiments. It is a miniature system-on-chip (SoC) that allows recording with simultaneous electrical microstimulation. This function has not been demonstrated before and enables precise, closed-loop neuromodulation. Neuronix represents recent advancement in brain technology and applies to both animal research and clinical applications.

Training-free compressed sensing for wireless neural recording

Signal compression is crucial for resource-constrained wireless neural recording applications with limited data bandwidth, and Compressed Sensing (CS) has successfully demonstrated its potential in this field. However, the conventional CS approaches rely on data-dependent and computationally intensive dictionary learning processes to find out the sparse representation of neural signals, and dictionary re-training is inevitable during real experiments. This paper proposes a training-free CS approach for wireless neural recording. By adopting the analysis model to enforce the signal sparsity and constructing a multi-order difference matrix as the analysis operator, it avoids the dictionary learning procedure and reduces the need for previously acquired data and computational complexity. In addition, a group weighted analysis 11-minimization method is developed to recover the neural signals. Experimental results reveal that the proposed approach outperforms the state-of-the-art CS methods for wireless neural recording.

A streaming PCA based VLSI chip for neural data compression

Local field potentials (LFPs) are popularly used in wireless neural interface due to its chronic stability and robustness against noise and radio interferences. On-chip data compression is advantageous that allows for integration with the recent low-power, low-data-rate wireless technologies to ensure reliable operations. In this paper, we propose a streaming principal component analysis (PCA) based algorithm and its microchip implementation to compress multichannel LFP data. The chip has been designed in a 65nm CMOS technology and occupies a silicon area of 0.06mm2. It has been tested with guinea pig auditory cortex data recorded with a multi-shank Neuro Nexus probe, where the chip can achieve an 8× compression ratio with ∼3% average reconstruction error, consuming 144nW per channel at a 0.5V power supply.

Deep compressive autoencoder for action potential compression in large-scale neural recording

OBJECTIVE Understanding the coordinated activity underlying brain computations requires large-scale, simultaneous recordings from distributed neuronal structures at a cellular-level resolution. One major hurdle to design high-bandwidth, high-precision, large-scale neural interfaces lies in the formidable data streams (tens to hundreds of Gbps) that are generated by the recorder chip and need to be online transferred to a remote computer. The data rates can require hundreds to thousands of I/O pads on the recorder chip and power consumption on the order of Watts for data streaming alone. One of the solutions is to reduce the bandwidth of neural signals before transmission. APPROACH We developed a deep learning-based compression model to reduce the data rate of multichannel action potentials. The proposed compression model is built upon a deep compressive autoencoder (CAE) with discrete latent embeddings. The encoder network of CAE is equipped with residual transformations to extract representative features from spikes, which are mapped into the latent embedding space and updated via vector quantization (VQ). The indexes of VQ codebook are further entropy coded as the compressed signals. The decoder network reconstructs spike waveforms with high quality from the quantized latent embeddings through stacked deconvolution. MAIN RESULTS Extensive experimental results on both synthetic and in vivo datasets show that the proposed model consistently outperforms conventional methods that utilize hand-crafted features and/or signal-agnostic transformations and compressive sensing by achieving much higher compression ratios (20-500×) and better or comparable reconstruction accuracies. Testing results also indicate that CAE is robust against a diverse range of imperfections, such as waveform variation and spike misalignment, and has minor influence on spike sorting accuracy. Furthermore, we have estimated the hardware cost and real-time performance of CAE and shown that it could support thousands of recording channels simultaneously without excessive power/heat dissipation. SIGNIFICANCE The proposed model can reduce the required data transmission bandwidth in large-scale recording experiments and maintain good signal qualities, which will be helpful to design power-efficient and lightweight wireless neural interfaces. We have open sourced the code implementation of the work at https://github.com/tong-wu-umn/spike-compression-autoencoder.

BVF: enabling significant on-chip power savings via bit-value-favor for throughput processors

Power reduction is one of the primary tasks for designing modern processors, especially for high-performance throughput processors such as GPU due to their high power budget. In this paper, we propose a novel circuit-architecture co-design scheme to harvest enormous power savings for GPU on-chip SRAM and interconnects. We propose a new 8T SRAM that exhibits asymmetric energy consumption for bit value 0/1, in terms of read, write and standby. We name this feature Bit-Value-Favor (BVF). To harvest the power benefits from BVF on GPUs, we propose three coding methods at architectural level to maximize the occurrence of bit-1s over bit-0s in the on-chip data and instruction streams, leading to substantial chip-level power reduction. Experimental results across a large spectrum of 58 representative GPU applications demonstrate that our proposed BVF design can bring an average of 21% and 24% chip power reduction under 28nm and 40nm process technologies, with negligible design overhead. Further sensitivity studies show that the effectiveness of our design is robust to DVFS, warp scheduling policies and different SRAM capacities. CCS CONCEPTS • Computer systems organization → Single instruction, multiple data; • Hardware → Static memory; Power estimation and optimization; Dynamic memory;

Hardware efficient, deterministic QCAC matrix based compressed sensing encoder architecture for wireless neural recording application

Wireless neural recording technologies are severely constrained by the limited energy efficiencies and telemetry bandwidth, while data compression or feature extraction techniques can be utilized to relax the burdens on the wireless data link. Compressed Sensing (CS) is an emerging approach for efficient data compression in wireless sensing applications. However, state-of-the-art CS encoder designs still lead to large area and energy overheads. This paper presents a novel CS encoder hardware design by incorporating deterministic measurement matrix, namely Quasi-Cyclic Array Code (QCAC) matrix, to improve overall area and power metrics over prior arts, while still preserving comparable signal recovery performance based on classic reconstruction algorithms. We demonstrate the advantages of the proposed QCAC-CS encoder design for spike data compression in neural recording application. Compared to the state-of-the-art CS encoder designs, QCAC-based CS encoder achieves on average (with compression ratio ranging from 0.0625 to 0.25) 42.7% and 49.5% reduction in encoder area and total power consumption, respectively. And the compressed spikes from the QCAC-CS encoder can be recovered with comparable performance toward random matrix based CS encoder designs.

A programmable fully-integrated microstimulator for neural implants and instrumentation

This paper presents a fully-integrated stimulator chip for electrical microstimulation. The device is designed in a high-voltage process that allows up to 20V power supply and 19V output voltage compliance. A broad range of current-mode stimulation waveforms and patterns can be generated, including symmetrical/asymmetrical, biphasic/monophasic, and pulse train stimuli. The current amplitude, pulse width, and stimulation rate are adjustable from 0.5μA to 2mA, 100μs to 4ms, and 0.1Hz to 200Hz, respectively. Two complementary charge-balancing techniques are integrated to reduce residual voltage and stimulation artifacts. In in vitro experiments, the stimulator is demonstrated to trigger neural spikes, modulate neuronal firing rate, and alter mesoscopic neuronal activity. The results suggest the proposed microstimulator can support a wide variety of neuroscience experiments that require electrical microstimulation.