Wilfried Haensch

Sub-10 nm carbon nanotube transistor.

This first demonstration of CNT transistors with channel lengths down to 9 nm shows substantially better scaling behavior than theoretically expected. Numerical simulations suggest that a possible explanation for the surprisingly good performance is a result of the gate modulating both the charge in the channel and in the contact regions. The unprecedented performance should ignite exciting new research into improving the purity and placement of nanotubes, as well as optimizing CNT transistor structure and integration. Results from aggressively scaling these molecular-channel transistors exhibit their strong suitability for a low-voltage, high-performance logic technology.

Silicon CMOS devices beyond scaling

To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be designed for exceptional stability and write margins, array-level implications must also be considered to achieve a viable memory solution. These constraints can be addressed by modifying traditional 6T-SRAM techniques and conceding some design complexity and area penalties. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies. The proposed 8T solution is demonstrated in a high-performance 32 kb subarray designed in 65 nm PD-SOI CMOS that operates at 5.3 GHz at 1.2 V and 295 MHz at 0.41 V.

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

Metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation. Devices satisfy the following metal-gate technology requirements: ideal mobility, low gate leakage, high transconductance, competitive I/sub on//I/sub off/, and adjustable V/sub t/. Six silicide gate materials are presented, as well as two silicide workfunction engineering methods.

Ultralow-voltage, minimum-energy CMOS

Energy efficiency has become a ubiquitous design requirement for digital circuits. Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy use. In this work, we review circuit behavior at low voltages, specifically in the subthreshold (Vdd < Vth) regime, and suggest new strategies for energy-efficient design. We begin with a study at the device level, and we show that extreme sensitivity to the supply and threshold voltages complicates subthreshold design. The effects of this sensitivity can be minimized through simple device modifications and new device geometries. At the circuit level, we review the energy characteristics of subthreshold logic and SRAM circuits, and demonstrate that energy efficiency relies on the balance between dynamic and leakage energies, with process variability playing a key role in both energy efficiency and robustness. We continue the study of energy-efficient design by broadening our scope to the architectural level. We discuss the energy benefits of techniques such as multiple-threshold CMOS (MTCMOS) and adaptive body biasing (ABB), and we also consider the performance benefits of multiprocessor design at ultralow supply voltages.

Interconnects in the third dimension: design challenges for 3D ICs

Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two- dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

In this letter, we report self-aligned n-channel germanium (Ge) MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate electrode. Excellent off-state current is achieved through the reduction of junction leakage. For the first time, we have demonstrated an n-channel Ge MOSFET with a subthreshold slope of 150 mV/dec and an on-off current ratio of /spl sim/10/sup 4/.

Extreme scaling with ultra-thin Si channel MOSFETs

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

The effective drive current in CMOS inverters

A simple but accurate expression for the effective drive current, I/sub eff/, for CMOS inverter delay is obtained. We show that the choice I/sub eff/=(I/sub H/+I/sub L/)/2, where I/sub L/=I/sub ds/(V/sub gs/=V/sub dd//2,V/sub ds/=V/sub dd/), and I/sub H/=I/sub ds/(V/sub gs/=V/sub dd/,V/sub ds/=V/sub dd//2) is defined, accurately predicts inverter delay when tested against compact models over a variety of conditions and against hardware results in 90 nm node technology. Furthermore, this definition of I/sub eff/ accurately captures the delay behavior of non-traditionally scaled devices, where mobility and V/sub T//V/sub dd/ are scaled in neither a regular nor uniform manner.

Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.