George S. Tulevski

Tunable infrared plasmonic devices using graphene/insulator stacks

Superlattices are artificial periodic nanostructures which can control the flow of electrons. Their operation typically relies on the periodic modulation of the electric potential in the direction of electron wave propagation. Here we demonstrate transparent graphene superlattices which can manipulate infrared photons utilizing the collective oscillations of carriers, i.e., plasmons of the ensemble of multiple graphene layers. The superlattice is formed by depositing alternating wafer-scale graphene sheets and thin insulating layers, followed by patterning them all together into 3-dimensional photonic-crystal-like structures. We demonstrate experimentally that the collective oscillation of Dirac fermions in such graphene superlattices is unambiguously nonclassical: compared to doping single layer graphene, distributing carriers into multiple graphene layers strongly enhances the plasmonic resonance frequency and magnitude, which is fundamentally different from that in a conventional semiconductor superlattice. This property allows us to construct widely tunable far-infrared notch filters with 8.2 dB rejection ratio and terahertz linear polarizers with 9.5 dB extinction ratio, using a superlattice with merely five graphene atomic layers. Moreover, an unpatterned superlattice shields up to 97.5% of the electromagnetic radiations below 1.2 terahertz. This demonstration also opens an avenue for the realization of other transparent mid- and far-infrared photonic devices such as detectors, modulators, and 3-dimensional meta-material systems.The collective oscillation of carriers--the plasmon--in graphene has many desirable properties, including tunability and low loss. However, in single-layer graphene, the dependence on carrier concentration of both the plasmonic resonance frequency and magnitude is relatively weak, limiting its applications in photonics. Here, we demonstrate transparent photonic devices based on graphene/insulator stacks, which are formed by depositing alternating wafer-scale graphene sheets and thin insulating layers, then patterning them together into photonic-crystal-like structures. We show experimentally that the plasmon in such stacks is unambiguously non-classical. Compared with doping in single-layer graphene, distributing carriers into multiple graphene layers effectively enhances the plasmonic resonance frequency and magnitude, which is different from the effect in a conventional semiconductor superlattice and is a direct consequence of the unique carrier density scaling law of the plasmonic resonance of Dirac fermions. Using patterned graphene/insulator stacks, we demonstrate widely tunable far-infrared notch filters with 8.2 dB rejection ratios and terahertz linear polarizers with 9.5 dB extinction ratios. An unpatterned stack consisting of five graphene layers shields 97.5% of electromagnetic radiation at frequencies below 1.2 THz. This work could lead to the development of transparent mid- and far-infrared photonic devices such as detectors, modulators and three-dimensional metamaterial systems.

Sub-10 nm carbon nanotube transistor.

This first demonstration of CNT transistors with channel lengths down to 9 nm shows substantially better scaling behavior than theoretically expected. Numerical simulations suggest that a possible explanation for the surprisingly good performance is a result of the gate modulating both the charge in the channel and in the contact regions. The unprecedented performance should ignite exciting new research into improving the purity and placement of nanotubes, as well as optimizing CNT transistor structure and integration. Results from aggressively scaling these molecular-channel transistors exhibit their strong suitability for a low-voltage, high-performance logic technology.

Chemical doping and electron-hole conduction asymmetry in graphene devices.

We investigate poly(ethylene imine) and diazonium salts as stable, complementary dopants on graphene. Transport in graphene devices doped with these molecules exhibits asymmetry in electron and hole conductance. The conductance of one carrier is preserved, while the conductance of the other carrier decreases. Simulations based on nonequilibrium Greens function formalism suggest that the origin of this asymmetry is imbalanced carrier injection from the graphene electrodes caused by misalignment of the electrode and channel neutrality points.

Chemical doping of large-area stacked graphene films for use as transparent, conducting electrodes

Graphene is considered a leading candidate to replace conventional transparent conducting electrodes because of its high transparency and exceptional transport properties. The effect of chemical p-type doping on graphene stacks was studied in order to reduce the sheet resistance of graphene films to values approaching those of conventional transparent conducting oxides. In this report, we show that large-area, stacked graphene films are effectively p-doped with nitric acid. The doping decreases the sheet resistance by a factor of 3, yielding films comprising eight stacked layers with a sheet resistance of 90 Omega/(square) at a transmittance of 80%. The films were doped either after all of the layers were stacked (last-layer-doped) or after each layer was added (interlayer-doped). A theoretical model that accurately describes the stacked graphene film system as a resistor network was developed. The model defines a characteristic transfer length where all the channels in the graphene films actively contribute to electrical transport. The experimental data shows a linear increase in conductivity with the number of graphene layers, indicating that each layer provides an additional transport channel, in good agreement with the theoretical model.

Toward High-Performance Digital Logic Technology with Carbon Nanotubes

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moores law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling. This review examines the potential performance advantages of a CNT-based computing technology, outlines the remaining challenges, and describes the recent progress on these fronts. Although overcoming these issues will be challenging and will require a large, sustained effort from both industry and academia, the recent progress in the field is a cause for optimism that these materials can have an impact on future technologies.

Infrared Spectroscopy of Wafer-Scale Graphene

We report spectroscopy results from the mid- to far-infrared on wafer-scale graphene, grown either epitaxially on silicon carbide or by chemical vapor deposition. The free carrier absorption (Drude peak) is simultaneously obtained with the universal optical conductivity (due to interband transitions) and the wavelength at which Pauli blocking occurs due to band filling. From these, the graphene layer number, doping level, sheet resistivity, carrier mobility, and scattering rate can be inferred. The mid-IR absorption of epitaxial two-layer graphene shows a less pronounced peak at 0.37 ± 0.02 eV compared to that in exfoliated bilayer graphene. In heavily chemically doped single-layer graphene, a record high transmission reduction due to free carriers approaching 40% at 250 μm (40 cm(-1)) is measured in this atomically thin material, supporting the great potential of graphene in far-infrared and terahertz optoelectronics.

High purity isolation and quantification of semiconducting carbon nanotubes via column chromatography.

The isolation of semiconducting carbon nanotubes (CNTs) to ultrahigh (ppb) purity is a prerequisite for their integration into high-performance electronic devices. Here, a method employing column chromatography is used to isolate semiconducting nanotubes to 99.9% purity. The study finds that by modifying the solution preparation step, both the metallic and semiconducting fraction are resolved and elute using a single surfactant system, allowing for multiple iterations. Iterative processing enables a far more rapid path to achieving the level of purities needed for high performance computing. After a single iteration, the metallic peak in the absorption spectra is completely attenuated. Although absorption spectroscopy is typically used to characterize CNT purity, it is found to be insufficient in quantifying solutions of high purity (>98 to 99%) due to low signal-to-noise in the metallic region of ultrahigh purity solutions. Therefore, a high throughput electrical testing method was developed to quantify the degree of separation by characterizing ∼4000 field-effect transistors fabricated from the separated nanotubes after multiple iterations of the process. The separation and characterization methods described here provide a path to produce the ultrahigh purity semiconducting CNT solutions needed for high performance electronics.

Carbon Nanotube Complementary Wrap-Gate Transistors

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs. Further, both n- and p-type transistors were realized by using the appropriate gate dielectric-HfO2 yielded n-type and Al2O3 yielded p-type-with quantum simulations used to explore the impact of important device parameters on performance. These discoveries not only provide a promising platform for further research into gate-all-around CNT devices but also demonstrate that scalable digital switches with realistic technological potential can be achieved with carbon nanotubes.

End-bonded contacts for carbon nanotube transistors with low, size-independent resistance

Making better small contacts Semiconducting single-walled carbon nanotubes have potential size and conductivity advantages over silicon for making smaller transistors. However, as metal electrical contacts decrease in size, the associated resistance increases to impractical values. Cao et al. reacted molybdenum films with semiconducting carbon nanotubes to create a carbide contact. The resistance of these contacts remained low even for 10-nm-scale contacts. Science, this issue p. 68 A covalent contact formed by the reaction of molybdenum and semiconducting carbon nanotubes has no Schottky barrier. Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes. A high-performance SWNT transistor was fabricated with a sub–10-nanometer contact length, showing a device resistance below 36 kilohms and on-current above 15 microampere per tube. The p-type end-bonded contact, formed through the reaction of molybdenum with the SWNT to form carbide, also exhibited no Schottky barrier. This strategy promises high-performance SWNT transistors, enabling future ultimately scaled device technologies.

Variability in carbon nanotube transistors: improving device-to-device consistency.

The large amount of hysteresis and threshold voltage variation in carbon nanotube transistors impedes their use in highly integrated digital applications. The origin of this variability is elucidated by employing a top-coated, hydrophobic monolayer to passivate bottom-gated devices. Compared to passivating only the supporting substrate, it is found that covering the nanotube channel proves highly effective and robust at improving device-to-device consistency-hysteresis and threshold voltage variation are reduced by an average of 84 and 53%, respectively. The effect of gate and drain-source bias on hysteresis is considered, showing strong dependence that must be accounted for when analyzing the effectiveness of a passivation layer. These results provide both key insight into the origin of variability in carbon nanotube transistors and a promising path for resolving this significant obstacle.