Willi Gerlach

Multistep field plates for high-voltage planar p-n junctions

Multistep field plates are often used to improve the blocking capability of planar p-n junctions. The electric field at the semiconductor surface below the field plate peaks, however, at every edge of the dielectric. In order to achieve the highest possible breakdown voltage at a given number of steps in the dielectric, their heights have to be adjusted as to equalize the corresponding peak fields. For this purpose, an analytical model has been developed, which relates the peak field to the geometrical and physical parameters of the structure. From this, a systematic method has been derived for designing multistep field plates with equal peak fields at the steps. By applying this method to a planar p-n junction the blocking capability was increased from 23% without field plates to more than 89% of the bulk breakdown voltage. >

The contour of an optimal field plate-an analytical approach

An analytical relationship has been developed to calculate the field distribution at the semiconductor surface of an MOS structure with a finite rectangular metal electrode for the deep depletion mode. This relationship has been verified using two-dimensional numerical calculations. A further result of this model is a formula for the contour of an optimal field electrode. >

On the blocking capability of a planar p-n junction under the influence of a high-voltage interconnection - a 3-D simulation

The routing of interconnections along the surface of a high-voltage IC presents one of the major issues for the IC designer. A special problem appears, if the interconnection can stay under a high-voltage signal and has to cross the boundaries of p-n junctions. In this paper, the influence of a high-voltage interconnection (HVI) on the blocking capability of a planar p-n junction including a JTE-design is investigated numerically by solving Poissons equation under the depletion approximation. Recent 2-D simulations have shown, that a HVI crossing the space charge region within a distance smaller than 5 /spl mu/m reduces the breakdown voltage drastically. However, these calculations ignored the limited lateral extension of real interconnection stripes and tend to overestimate its influence. As exhibited by the 3-D simulations in this paper, the influence of the stripe width can be ignored only for such structures, where the width of the stripe is in the same order of magnitude as the depletion layer width. For smaller stripe widths the influence of the HVI is lower. The dependence of the breakdown voltage on the stripe width is investigated for different distances between the HVI and the semiconductor surface.

Calculation of the blocking capability of SOI power devices under the influence of interconnections

Abstract Numerical results are presented on the influence of a high-voltage interconnection on the blocking voltage of planar p-n junctions. The calculations are performed by a simulation program, which solves the Poisson equation using the depletion model. First, a device with a junction termination extension design was investigated. As the interconnection crosses the space charge region (SCR) in a small distance of only a few micrometres the field distribution is disturbed appreciably. Three-dimensional (3D) computations show that the lateral width of the metal stripe plays an important role in the breakdown voltage. If the width of the stripe is of the same order as the vertical width of the SCR the negative influence from the interconnection is maximal. Only for this case are 2D simulations justified. For this special instance 2D simulations of SOI devices with interconnection are performed.