Elmar Falck

Multistep field plates for high-voltage planar p-n junctions

Multistep field plates are often used to improve the blocking capability of planar p-n junctions. The electric field at the semiconductor surface below the field plate peaks, however, at every edge of the dielectric. In order to achieve the highest possible breakdown voltage at a given number of steps in the dielectric, their heights have to be adjusted as to equalize the corresponding peak fields. For this purpose, an analytical model has been developed, which relates the peak field to the geometrical and physical parameters of the structure. From this, a systematic method has been derived for designing multistep field plates with equal peak fields at the steps. By applying this method to a planar p-n junction the blocking capability was increased from 23% without field plates to more than 89% of the bulk breakdown voltage. >

The contour of an optimal field plate-an analytical approach

An analytical relationship has been developed to calculate the field distribution at the semiconductor surface of an MOS structure with a finite rectangular metal electrode for the deep depletion mode. This relationship has been verified using two-dimensional numerical calculations. A further result of this model is a formula for the contour of an optimal field electrode. >

Destruction behavior of power diodes beyond the SOA limit

Simulation results show how cathode-side filaments may trigger a thermal runaway at the end of a reverse-recovery period of diodes turned off with extremely high current rates. The mechanism is not essentially affected by the edge termination if an appropriate design is chosen. While multiple avalanche-induced filaments may appear during the reverse-recovery period, at the end of the turn-off phase a single “winning” filament carries the total current. This can result in a local melting of the diode. The appearance of a cathode-side filament by itself does not necessarily lead to the diode destruction. However, a high thermal carrier generation rate can result in an uncontrollable increase of the current density in a single filament connecting the anode and the cathode contact. It is shown t hat the reverse-recovery charge as a function of the dc-link voltage shows a characteristic super-linear increase below the critical value dc-link voltage at which the diode current increases uncontrollably.

Cathode-Side Current Filaments in High-Voltage Power Diodes Beyond the SOA Limit

An analysis of the plasma front velocities during turnoff of a power diode is used to explain the differences between the formation and the behavior of cathode-side and anode-side filaments. Device simulations show, how cathode-side filaments may trigger a thermal runaway at the end of a reverse-recovery period of diodes turned off with extremely high current rates operating the diode in a regime far away from the safe operating area. From the transient voltage curve, the analysis of the reverse-recovery charge as a function of the dc-link voltage and an analysis of the turnoff transients in the current-voltage phase space, it is, however, deduced that the appearance of a cathode-side filament by itself does not necessarily lead to diode destruction. The transformation of the initially avalanche-generated filaments into filaments that are essentially driven by thermal mechanism seems to be a further important condition for device destruction.

On the blocking capability of a planar p-n junction under the influence of a high-voltage interconnection - a 3-D simulation

The routing of interconnections along the surface of a high-voltage IC presents one of the major issues for the IC designer. A special problem appears, if the interconnection can stay under a high-voltage signal and has to cross the boundaries of p-n junctions. In this paper, the influence of a high-voltage interconnection (HVI) on the blocking capability of a planar p-n junction including a JTE-design is investigated numerically by solving Poissons equation under the depletion approximation. Recent 2-D simulations have shown, that a HVI crossing the space charge region within a distance smaller than 5 /spl mu/m reduces the breakdown voltage drastically. However, these calculations ignored the limited lateral extension of real interconnection stripes and tend to overestimate its influence. As exhibited by the 3-D simulations in this paper, the influence of the stripe width can be ignored only for such structures, where the width of the stripe is in the same order of magnitude as the depletion layer width. For smaller stripe widths the influence of the HVI is lower. The dependence of the breakdown voltage on the stripe width is investigated for different distances between the HVI and the semiconductor surface.

Electro-Thermal Simulation of Current Filamentation in 3.3-kV Silicon p + - n - - n + Diodes with Differenth Edge Terminations

We investigate the current filamentation behavior during reverse recovery in high-voltage 3.3-kV silicon p+ - n- - n+ diodes with transient S-shape negative differential resistance characteristics. The transient I-U-bistability occuring in the reverse recovery period leads to a non-uniform, current distribution in the diodes when they are turned off with a high current rate di/dl. In this paper we compare the filament behavior of diodes without any edge termination with that of diodes providing a non-optimized JTE (junction termination extension), an optimized JTE, and a beveled edge termination by means of isothermal and electro-thermal device simulations. The observed differences are explained by analyzing the transient electric-field, current-density and temperature distributions in the devices