William A. Rogers

Fault simulation in a distributed environment

Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<<ETX>>

Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations

This paper presents the technique of concurrent hierarchical fault simulation, a performance model, and two hierarchical optimization techniques to enhance fault simulator performance. The mechanisms for these enhancements are demonstrated with a performance model and are validated experimentally via CHIEFS, the Concurrent Hierarchical and Extensible Fault Simulator, and WRAP, an offline hierarchy compressor. Hieararchy-based fault partitioning and circuit reconfiguration are shown to improve simulator performance to O(n log n) under appropriate conditions. A decoupled fault modeling technique permits further performance improvements via a bottom-up hierarchy compression technique where macros of primitives are converted to single primitives. When combined, these techniques have produced a factor of 180 speedup on a mantissa multiplier. The performance model indicates that the speedup should increase with circuit size.

A test methodology for finite state machines using partial scan design

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.

High level hierarchical fault simulation techniques

This paper presents techniques for simulating directly from a hierarchical circuit description without flattening to the level of primitives. An overview of traditional fault simulation techniques is followed by details of the hierarchical techniques. The fault model is shown to be decoupled from the simulator programs through the use of a fault library. The fault library allows the user to mix both functional and technology-dependent fault models, which allows fault simulation and consequently test coverage estimation early in the design, with refinements in the fault model and test coverage as the design progresses. Thus testing problems can be detected early in the design process while they are much easier to correct. The circuit description language, SCALD, and the fault library language are described and illustrated with examples. The simulator initialization and execution phases are discussed in detail with emphasis on the unique data structures necessary for hierarchical simulation. The hierarchy provides a framework for an adaptive evaluation technique that speeds the evaluation of faulty machines. Initial performance measurements and experiences with the simulator indicate that hierarchical fault simulation is superior to traditional techniques.

A new design for testability method: Clock line control design

Clock line control (CLC) is proposed as a new design for testability (DT) technique which can transform a complex test generation problem into many small ones that are efficiently manageable by selectively clocking modules. Hardware overhead in CLC increases in proportion to the number of sequential modules rather than individual memory elements, which result in very low overhead. The sequential modules become combinational when their clocks are disabled, and they are efficiently handled by the test generator. Test generation proceeds by expanding multiple time frames for one sequential module at a time. The total number of states the test generator considers at one time is determined by the number of state variables in the clocked module instead of the entire circuit.

Hierarchical test pattern generation: a cost model and implementation

A cost model for and implementation of a hierarchical test generation technique are presented. The cost model is based on fundamental test generation activities such as implication, justification, and backtracking. The model shows that the cost of hierarchical test generation grows as G log G under some realistic assumptions, while the cost of gate-level test generation may grow as fast as G/sup 2/, where G is the number of gates in a circuit under test. This implies that hierarchical test generators should be much faster than flat test generators on large circuits. The implementation of the hierarchical test generation is fan-out-oriented and uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracing with high-level functional models. Experiments with three hierarchically described circuits show that hierarchical test generation is 1.5 to 8.9 faster than flat gate-level generation. >

Search strategy switching: cost model and an analysis of backtracking

Test generation algorithms contain search strategies which are used to control decision making when the algorithm encounters a choice of signal value, or what action to perform next. Our study of traditional search strategies used in automatic test pattern generation has led us to the observation that no single strategy is superior for all faults in a circuit and all circuits. Further experimentation led to the conclusion that a combination of search strategies provides better fault coverage and/or faster ATPG for a given backtrack limit. Instead of using just one strategy up to the backtrack limit, a primary strategy is used for the first half of the backtrack limit, then a secondary strategy is used for the second half of the backtrack limit. This article presents a qualitative ATPG cost model based on the number of test generation events, uses this model to explain why search strategy switching is faster, and shows experimental evidence to verify both the cost model and search strategy switching theory. The experiments were performed with the ISCAS circuits and our implementation of the FAN algorithm.

The impedance fault model and design for robust impedance fault testability

It is pointed out that advanced submicron CMOS processes result in failure mechanisms that tend to be increasingly analog in nature. They are not adequately covered by stuck-at, stuck-on, or stuck-open models. Furthermore, delay faults, spot defect models, and IDDQ approaches only cover restricted subsets of the dominant failure mechanisms. The impedance fault model forms a superset of all the above fault models while explicitly addressing the analog nature of the failures. An associated design methodology for robust impedance fault testability (DRIFT) provides robustly testable general structures with less area overhead than other transistor level DFT techniques and negligible speed penalties. DRIFT is especially well-suited for gate array, standard cell, and synthesized designs. The effects of process and device level variabilities of the IC are directly represented as variations of the channel impedance characteristics. The DRIFT techniques then transform the channel impedance difference into logic level changes at the CMOS structure output.<<ETX>>

FANHAT: fanout oriented hierarchical automatic test generation system

FANHAT, has been designed and implemented to accelerate test generation for digital circuits. FANHAT uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracking with high-level functional model. Experiments with three circuits show hierarchical test generation using FANHAT is 1.5 to 8.9 times faster than flat gate-level test generation.<<ETX>>

Enhancing temporal testability and its effects on design and test generation

Increasing controllability in the time dimension (CTD) helps test generation either by temporarily reducing the search space through freezing state variables or by simplifying the time-frame-expansion. CTD can be increased via controlling clock lines through a well defined DFT scheme, called clock line control (CLC). The design issues for controlling clock lines have been addressed. CLC can be extended to test delay faults without causing the test vector application problems as in scan design. Experimental results using ISCAS-89 circuits are shown. Better fault coverage with shorter ATG time have been achieved for the circuits with enhanced CTD