William D. Farwell

An experimental chip to evaluate test techniques: chip and experiment design

An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25 k gate CMOS Test Chip has been designed, manufactured (5491 devices),and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs.

A fault tolerant signal processing computer

A fault tolerant computer has been designed for radiation environments which employs COTS components. The use of radiation-tolerant but not fully hardened COTS devices provides significantly higher performance than specialty, fully hardened parts. The computer architecture consists of multiple, redundant processing nodes, each containing levels of internal redundancy, and multiple point-to-point communication ports on a crossbar switch. The nodes are linked together via ports to form a distributed crossbar network with inherent fault tolerance. A key attribute of the architecture is the provision for selectable levels of error detection and recovery. The trade-offs between performance and degree of fault tolerance can be dynamically adjusted to meet specific system needs and parts selection at any particular time.