Piero Franco

An experimental chip to evaluate test techniques experiment results

This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for CrossCheck, Very-Low-Voltage, IDDQ and delay tests are also given.

On-line delay testing of digital circuits

A new technique for on-line checking of digital systems is proposed. It is shown that, under certain timing restrictions, an off-line delay-fault testing method called Stability Checking can be used for on-line checking. Efficient CMOS on-line Stability Checker designs are presented, and an algorithm for meeting timing restrictions is described. Benchmark results are shown. On-line Stability Checkers detect errors caused by most common reliability failures and transients, and are shown to perform almost as well as duplication at a fraction of the hardware cost. Since outputs are checked independently, good diagnosability is possible.<<ETX>>

DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS

A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.

An experimental chip to evaluate test techniques: chip and experiment design

An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25 k gate CMOS Test Chip has been designed, manufactured (5491 devices),and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs.

Three-pattern tests for delay faults

To improve the quality of CMOS digital circuits, more complex fault models than single stuck-at have been proposed. This paper focuses on the effect of inaccurate delay modeling on delay fault testing. It is shown that accurate delay models are needed for effective delay fault testing. This is particularly important for large timing optimized circuits with many paths. Limitations of the path delay fault model are shown, and even the assumption that 2-pattern tests are sufficient for delay testing is shown to have limitations.<<ETX>>

Simple bounds on serial signature analysis aliasing for random testing

It is shown that the aliasing probability is bounded above by (1+ epsilon )/L approximately=1/L ( epsilon small for large L) for test lengths L less than the period, L/sub c/, of the signature polynomial; for test lengths L that are multiples of L/sub c/, the aliasing probability is bounded above by 1; for test lengths L greater than L/sub c/ and not a multiple of L/sub c/, the aliasing probability is bounded above by 2/(L/sub c/+1). These simple bounds avoid any exponential complexity associated with the exact computation of the aliasing probability. Simple bounds also apply to signature analysis based on any linear finite state machine (including linear cellular automaton). From these simple bounds it follows that the aliasing probability in a signature analysis design using beta intermediate signatures is bounded by ((1+ epsilon )/sup beta / beta /sup beta /)/L/sup beta /, for beta >

REFINED BOUNDS ON SIGNATURE ANALYSIS ALIASING FOR RANDOM TESTING

in previous work a simple bound, ~+2 , on the aliasing probability in serial signature analysis for a random test pattern of length L was derived. This simple bound is sharpened here by almost a factor of two. For serial signature analysis, it is shown that the I+& 1 aliasing probability is bounded above by - = L (E L small for large L) for test lengths L less than the period, Lc, of the signature polynomial. The simple bounds derived are compared with exact as well as experimentally measured aliasing probability values. It is conjectured that L-l is the best monotonic bound on the aliasing probability for serial signature analysis.

Bounds on signature analysis aliasing for random testing

Simple bounds on the aliasing probability for serial signature analysis are presented. To motivate the study, it is shown that calculation of exact aliasing is NP-hard and that coding theory does not necessarily help. It is shown that the aliasing probability is bounded above by 2/(L+2) for test lengths L less than the period, L/sub c/, of the signature polynomials; for test lengths L that are multiples of L/sub c/, the aliasing probability is bounded above by 1; and, for test lengths L greater than L/sub c/ and not a multiple of L/sub c/, the aliasing probability is bounded above by 2/(L/sub c/+1). These simple bounds avoid any exponential complexity associated with the exact computation of the aliasing probability. Simple bounds also apply to signature analysis based on any linear finite state machine (including linear cellular automata).<<ETX>>

Relating aliasing in signature analysis to test length and register design

Recently derived upper bounds on the aliasing probability for serial signature analysis using the Bernoulli error model are reviewed. Since the bit error probability p is unrestricted in general, upper bounds independent of p are emphasized. It is also shown that even for exhaustive testing, the aliasing probability for non-primitive polynomials with short periods does not reach its asymptotic value of all p.<<ETX>>

Test chip experiments at stanford CRC

The idea of the test chip experiments started in ITC 1991 [McCluskey 00]. We wanted to get actual tester data that would answer some questions about manufacturing test of digital ICs. The objective was to find out the relative effectiveness of different test techniques, such as stuck fault tests, delay tests, IDDq, etc.