William E. Dougherty

Metrics for structural logic synthesis

Routability or wiring congestion in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the routability irrespective of the placement algorithm used. Placement algorithms find optimal assignment of locations to the logic and do not have the ability to change the netlist structure. Significant decisions regarding the circuit structure are made early in synthesis such as during the technology independent logic optimization step. Optimizations in this step use literal count as a metric for optimization and do not adequately capture the intrinsic entanglement of the netlist. Two circuits with identical literal counts may have significantly different congestion characteristics post placement. In this paper, we motivate that a property of the network structure called adhesion can make a significant contribution to routing congestion. We then provide a metric to measure this property. We also show that adhesion as measured by this metric can be used in addition to literal counts to estimate and optimize post routing congestion early in the design flow.

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Transaction-Level models have emerged as an efficient way of modeling systems-on-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transaction-based power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.

Measurements for structural logic synthesis optimizations

Routability or wiring congestion in a very large scale integration chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the routability irrespective of the placement algorithm used. Placement algorithms find optimal assignments of locations to the logic and do not have the ability to change the netlist structure. Significant decisions regarding the circuit structure are made early in synthesis during the technology-independent logic-optimization step. Optimizations in this step use literal count as a metric for optimization and do not adequately capture the intrinsic entanglement of the netlist. Two circuits with identical literal counts may have significantly different congestion characteristics after placement. In this paper, we postulate that a property of the network structure called adhesion can make a significant contribution to routing congestion. We then provide a metric to measure this property. We evaluate the utility of adhesion as measured by this metric to estimate and optimize postrouting congestion early in the design flow. A heuristic for measuring adhesion is evaluated as well.