William G. Bliss

Finite word-length effects of pipelined recursive digital filters

Scattered look-ahead (SLA) pipelining is a new IIR filter structure that can achieve very high throughput, regardless of multiplier latency. However, the numerical properties of SLA have been largely unexplored. The authors analyze the finite word-length (FWL) performance of SLA filters under fixed-point arithmetic. To support this analysis, two new state variable descriptions (SVD) are introduced. First, a state variable based description especially suited for analysis of certain SLA structures, called the sectioned K and W description (SKWD), is defined by sectioning the noise contributions of the nonrecursive nodes. Second, a noncanonic state variable description (NCSVD) is introduced, which explicitly includes the pipelined delay variables in the state space. Roundoff noise (RON) and statistical coefficient quantization noise (SCQN) are derived under an independent pseudonoise source model, SCQN is shown to be interpretable as RON under the single length accumulation model, which enables the unification of RON and SCQN analysis. Analytic closed form solutions for first- and second-order direct form (DF) SLA filters are derived and compared to results from SLA minimum roundoff noise (MRON) structures. The SLA structures are all found to have generally good numerical properties, except that the DF SLA structure performs poorly in certain regions near the unit circle. However, the DF SLA structure actually performs better than the MRON form over much of the unit disk at a far smaller implementation cost. >

A very small sub-binary radix DAC for static pseudo-analog high-precision memory

A sub-binary radix digital-to-analog converter (DAC) which achieves high effective resolution in a small VLSI area is demonstrated and is shown to be especially well suited for certain static analog memory applications, including tunable analog circuits. An intentional sub-binary radix is used to create a redundant number system with radix less than two, while still using normal binary coefficients (on/off control). A current mode DAC with greater than ten bits effective resolution is implemented in only 41 mil/sup 2/ area in a 2 mu CMOS technology. A simple iterative algorithm to control (set) these nonlinear and nonmonotonic DACs is detailed.<<ETX>>

A tuning algorithm for digitally programmable continuous-time filters

This algorithm is based on estimates of filter characterization parameters based on the results of a system identification and subsequently calculated adjustments of the modeled controlling components. Simulations show this algorithm converges to a solution after iterations in the ideal case and attains good speed and accuracy even when parasitic effects are included in the system model. Simulations of the tuning of a sixth-order elliptic lowpass filter with 0.5-dB passband ripple designed to have a normalized cutoff frequency at 1 (rad/s) indicate that 0.501-dB passband ripple and 0.015% accuracy in the 3 dB band-edge can be achieved in the presence of typical parasitics.<<ETX>>

Limit cycle behavior of pipelined recursive digital filters

The important new class of pipelined IIR filters, called scattered look-ahead (SLA) filters, is analyzed for limit cycle behavior, including both overflow and quantization limit cycles. Direct form (DF), minimum roundoff noise (MRON) form and apparent direct form (ADF) are selected as basis structures of SLA filters. The z-domain is extensively searched as a function of the number of pipelining stages for limit cycle free regions, which is transferred from analytic parameter space results. In consequence, the DF SLA structure is proved to have merits implementing high Q filters except at certain regions near the unit circle, where the structure is highly susceptible to roundoff noise (RON) and coefficient quantization noise (CQN). DF and MRON based structures are compared for the purpose of reducing complexity or improving numerical performance. >

Comments on "Finite word-length effects of pipelined recursive digital filters" [with reply]

The author comments that it is generally inappropriate to use stochastic models for coefficient quantization errors in digital filters, as proposed by Chang and Bliss (see ibid., vol.42, p.1983-95, Aug. 1994), since the associated effects are deterministic and amenable to linear analysis. Chang et. al. reply that the statistical analysis of coefficient quantization noise in digital filters is a useful technique because it gives theoretical and practical results without resorting to lengthy case-by-case trials. The realization problem of digital filters can thus be simplified analytically by statistical approaches. Furthermore, statistical approaches have an advantage of supplying unified tools for round-off and coefficient quantization noise.

High precision in situ tuning of monolithic continuous time leapfrog filters

The authors present an in situ method of tuning analog continuous time monolithic integrated circuit filters which achieves high precision when applied to leapfrog structures. The in situ method directly tunes selected subcircuits of the filter, so that neither accurate capacitor nor gain matching of circuit components is required. High precision is achieved by directly tuning highly isolated simple subsections of the filter. Two tuning methods are considered. First, lossless two-integrator loops are tuned by their oscillation frequencies. Secondly, single time constant circuits are tuned by observing magnitudes at cut-off frequencies. The tuning overhead of the in situ method is shown to be reasonable, much less than with the general programmable methods.<<ETX>>

The roundoff noise of pipelined scattered look-ahead IIR digital filters with decomposition

Scattered look-ahead (SLA) with power-of-two decomposition has been proposed for high-throughput recursive digital filters. The roundoff noise of first- and second-order minimum roundoff noise structures and direct-form SLA structures is determined. An improvement over previous results is obtained by enforcing proper scaling and including nonrecursive section noise.<<ETX>>

A high-frequency BiCMOS buffer for testing analog ICs

Debugging large mixed-signal ICs involves monitoring several critical internal nodes that connect to various sub-systems. Direct accessing of these nodes may or may not be feasible depending on the drive capability of the node involved. Hence, a suitable on-chip buffer that facilitates the proper monitoring of the internal node is necessary. A compact BiCMOS buffer to accomplish this is presented. The buffer has an area of less than 0.09 mm/sup 2/, and has a 3-dB bandwidth in excess of 50 MHz. Total DC operating current is 1.8 mA at 5-V supply.<<ETX>>

Roundoff and coefficient quantization noise of pipelined scattered look-ahead filters with decomposition

Unified statistical coefficient quantization (SCQ) and round-off noise (RON) analysis for a fixed-point arithmetic model is applied to scattered look-ahead (SLA) with power-of-two decomposition filters. Assumptions under which noise power due to SCQ is the same as RON under single length accumulation are derived. Analytical results are derived for first-and second-order direct-form (DF) and minimum roundoff noise (MRON) basis filters which contradict previous claims. The application of SLA is shown to slightly increase noise for poles near z=0 and to generally decrease noise near mod z mod =1, except that the noise of DF SLA increases greatly for small regions near mod z mod =1 due to closely spaced poles.<<ETX>>

Efficient and reliable VLSI algorithms and architectures for the discrete Fourier transform

The design of both area-efficient and reliable VLSI arrays for computation of the complex N-point discrete Fourier transform (DFT) is considered. C.D. Thompsons VLSI model of computation (1979) is used to quantify the area required by wiring and the achievable period. Four architectures using the fast two-dimensional (2-D) algorithm for the DFT that achieve the maximum throughput per chip area are presented. The first two use N-element 2-D meshes requiring N+2N/sup 3/2/ multiplications and 1+2 square root N periods per DFT. The first uses in place data I/O and can be made systolic with Goertzels algorithm. The second is systolic with row parallel I/O. The third and fourth architectures both use pipelined DFT blocks of length square root N connected by a pipelined matrix transposer. The third uses systolic 2-D meshes for the short DFTs with period square root N. The fourth uses pipelined butterfly networks implementing standard FFT algorithms for the short DFTs, but only N(1+log/sub 2/ N) multiplications per DFT, thus preserving maximum throughput per unit area. The technique of algorithm-based fault-tolerance applies directly to all four architectures with only fractional redundant overhead.<<ETX>>