William J. Lewis

Functional verification of the IBM system z10 processor chipset

This paper describes the comprehensive verification effort of the IBM System z10™ processor chipset, which consists of the z10™ quad-core central processor chip and the companion z10 symmetric multiprocessor (SMP) chip. The z10 processor chipset represented a significant redesign of its predecessor and thus presented a new challenge to ensure complete functional correctness of the product before the construction of actual system hardware. The z10 microprocessor pipeline was completely redesigned to support a doubling of the operating frequency. It also includes new hardware performance features, such as enhanced branch prediction, a reoptimized cache hierarchy, hardware-based prefetching, and a hardware implementation of decimal floating-point arithmetic in IEEE formats. In addition, there were significant hardware changes in the SMP storage hierarchy for optimized data latency performance. These changes include a new system topology, interprocessor book protocol, larger SMP size, and various aggressive cache ownership schemes. Key verification innovations are described, and a direct relationship to improved z10 system quality is provided for most cases.

Functional verification of the z990 superscalar, multibook microprocessor complex

This paper describes the verification methods and techniques that were established to verify the microarchitecture and architectural correctness of the z990 microprocessor and storage subsystem. The ring-based, four-book storage subsystem links 64 superscalar microprocessors together in this system. The verification process started at the unit level, which focused on the correctness of the microarchitecture, and then proceeded to the element level to verify the architectural correctness of the microprocessor and storage subsystem. After successfully completing element stress testing, the components were combined and verified at the system level. Since the methods used at system-level verification were much the same as the ones used on the CMOS-based IBM S/390® Parallel Enterprise Server G4, the focus of this paper is on the work done at the unit and element levels.

Key advances in the presilicon functional verification of the IBM zEnterprise microprocessor and storage hierarchy

This paper highlights key advances in the presilicon verification effort of the IBM zEnterprise® 196 (z196) microprocessor and storage hierarchy. It focuses on the unique set of verification challenges as well as the process innovations that address them. At the time of product launch, the z196 system represented the industrys fastest and most scalable enterprise system, with up to 80 customer-configurable out-of-order core processors operating at 5.2 GHz. In addition to offering industry-leading performance, the z196 system builds upon its leadership in reliability by introducing a new redundant array of independent memory (RAIM) technology into its memory subsystem. The new product features in this system drove innovations in all aspects of processor functional verification, including stimulus generation, functional checking, debugging, and coverage. A new hybrid RAIM verification methodology, which includes both formal and random methods, is described. Many process and methodology improvements were made to improve developmental collaboration across a global team. These enhancements include a simulation development environment that uses common shared components across functional partitions, as well as a shared cache loader that was used across multiple environments. We also present a self-configuring test-case generation process that focused on the coverage of functional stimulus.