William L. Bircher

Runtime identification of microprocessor energy saving opportunities

High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the solution of these problems by presenting: linear regression models for power consumption and a detailed study of energy efficiency in a modern out-of-order superscalar microprocessor. These simple (2-input) yet accurate (2.6% error) models provide a valuable tool for identifying opportunities to apply power saving techniques such as clock throttling and dynamic voltage scaling (DVS). Also, future work in improving energy efficiency is motivated by a detailed analysis of SPEC CPU 2000 workloads. The vast majority of workloads are found to yield very low energy efficiency due to the frequency of level two (L2) cache misses and misspeculated instructions.

Predictive power management for multi-core processors

Predictive power management provides reduced power consumption and increased performance compared to reactive schemes. It effectively reduces the lag between workload phase changes and changes in power adaptations since adaptations can be applied immediately before a program phase change. To this end we present the first analysis of prediction for power management under SYSMark2007. Compared to traditional scientific/computing benchmarks, this workload demonstrates more complex core active and idle behavior. We analyze a table based predictor on a quad-core processor. We present an accurate runtime power model that accounts for fine-grain temperature and voltage variation. By predictively borrowing power from cores, our approach provides an average speedup of 7.3% in SYSMark2007.

Core-Level Activity Prediction for Multicore Power Management

Existing power management techniques operate by reducing performance capacity (frequency, voltage, size) when performance demand is low. In the case of multicore systems, the performance and power demand is the aggregate demand of all cores in the system. Monitoring aggregate demand makes detection of phase changes difficult since aggregate phase behavior obscures the underlying phases generated by the workloads on individual cores. This causes suboptimal power management and over-provisioning of power resources. In this paper, we address these problems through core-level, activity prediction. The core-level view makes detection of phase changes more accurate, yielding more opportunities for efficient power management. Due to the difficulty in anticipating activity level changes, existing operating system power management strategies rely on reaction rather than prediction. This causes sub-optimal power and performance since changes in performance capacity by the power manager lag changes in performance demand. To address this problem we propose the periodic power phase predictor (PPPP). This activity level predictor decreases SYSMark 2007 processor power consumption by 5.4% and increases performance by 3.8% compared to the reactive scheme used in Windows Vista operating system. Applying the predictor to the prediction of processor power, we improve accuracy by 4.8% compared to a reactive scheme.

Power phase variation in a commercial server workload

Many techniques have been developed for adaptive power management of computing systems. These techniques rely on the presence of varying power phases to detect opportunities for adaptation. However, little information is available regarding the extent of power phases in real systems. This paper illustrates available power phases ranging from 1 millisecond to 1 second using a commercial workload running on enterprise class hardware. Data is obtained using a server instrumented for power measurement at the subsystem level. The analysis shows that chipset, memory and disk subsystems have the most homogenous phase behavior with greater than 71% of samples within phases of 100 milliseconds or shorter. In contrast, CPU and I/O subsystems have much more variation with only 26% of samples within phases of 10 milliseconds or shorter

Automating Stressmark Generation for Testing Processor Voltage Fluctuations

Rapid current changes (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. To test a processors resilience to such errors and determine appropriate operating conditions, engineers generally create manual di/dt stressmarks that have large current variations at close to the power distribution networks resonance frequency to induce large voltage droops. This process is time-consuming and might need to be repeated several times to generate appropriate stressmarks for different system conditions (for example, different frequencies or di/dt throttling mechanisms). Furthermore, generating efficient di/dt stressmarks for multicore processors is difficult because of their complexity and synchronization issues. In this article, the authors measure and analyze di/dt issues on state-of-the-art multicore x86 systems. They present an automated di/dt stressmark generation framework called Audit to generate di/dt stressmarks quickly and effectively for multicore systems.