William McMahon

Reliability scaling issues for nanoscale devices

We discuss two specific scaling issues that can result in qualitative changes in device reliability prediction for nanoscale devices. The first of these involves a rapid increase in early failures due to a distribution of activation energies of defect precursors. We show that the slopes of the failure functions for hot carrier interface state generation (HCI) and time-dependent dielectric breakdown (TDDB) have simple physical interpretations in terms of a geometrical factor and the activation energy distribution width. The second issue involves a transition from single to multiple electrons causing individual defects. This picture allows simple physical explanations for the larger HCI damage in NMOS versus PMOS, the anomalous isotope effect of activation energies for HCI in the lucky electron model, and the observed power law dependence of the time to breakdown versus voltage for TDDB for ultrathin oxides.

Theory of channel hot-carrier degradation in MOSFETs

Abstract A critical but still poorly understood process in metal-oxide-semiconductor field-effect transistors (MOSFETs) is stress-induced changes in device threshold voltage, channel conductance, etc. which limit the operating lifetimes of the transistors. However, the degradation characteristics of deep-submicron MOSFETs, the widely demonstrated deuterium/hydrogen isotope effect, and the related results of scanning-tunneling microscopy (STM)-based depassivation experiments on silicon–vacuum interfaces are providing new insights into the degradation of MOSFETs via, at least, depassivation of the silicon-oxide interface. In this manuscript, we review the basic mechanisms of depassivation, suggest disorder-induced variations in the threshold energies for silicon–hydrogen/deuterium bond breaking as a possible explanation for observed sublinear time dependencies for degradation below t 0.5 , and show that excitation of the vibrational modes of the bonds could play a significant role in the continuing degradation of deep-submicron MOSFETs operated at low voltages.

Simulation of Si-SiO/sub 2/ defect generation in CMOS chips: from atomistic structure to chip failure rates

We present a theory for Si-SiO/sub 2/ defect generation related to hydrogen activation by hot electrons. Starting from atomistic considerations, we first explain the time dependence of degradation particularly at short-times. We show that this time dependence is intimately linked to variations of activation energies. These variations are then used to develop a theory for device failure times that includes detailed considerations of enhanced latent failure rates for deep-submicron devices. With this theory, we can connect experiments of degradation at short-times to latent failure rates which are difficult to assess otherwise.

The physics of determining chip reliability

We have indicated the necessity for using statistical models to determine the reliability of deep-submicron MOSFETs. We have presented a methodology by which the reliability can be determined from short-time tests if the defect generation statistics are linked to variations in defect activation energies. We have shown that enhanced latent failures follow from our model for deep-submicron MOSFETs. Therefore, more stringent reliability standards are required, which can be validated by the use of short-time tests. Our model provides the means to calculate these novel reliability demands quantitatively.

A Multi-Carrier Model for Interface Trap Generation

We discuss the need for a multiple vibrational model of interface trap generation. Using first order perturbative scattering theory we derive the effect of vibrationally excited phonon modes on the electronic transition which is estimated to be responsible for interface state generation. We derive a multiple vibrational model which explains the observed change in device lifetime vs. source-drain current.

Impact of Scaling on CMOS Chip Failure Rate,and Design Rules for Hot Carrier Reliability

Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy distribution, as it causes an increased probability of smaller devices having lower activation thresholds and therefore faster activation times. Further, we quantify the voltage shift necessary to overcome the decreased yield due to the increased number of early device failures, and show, for 0.1 μm MOSFET scaling, that this shift can be a considerable fraction of the conventionally designed supply voltage.

Modeling failure modes for submicron devices

As CMOS technology scales down to the regime where atomic size becomes significant, it has become increasingly important to take a physics-of-failure approach to device design by understanding the underlying mechanisms of MOSFET degradation. We give a model which describes the time dependence of degradation of a general class of failure modes, applying the model specifically to hot-electron interface-state generation. With several typical measurements of device degradation characteristics, this model can be used to derive the failure function and extract the Weibull parameter for failure modes in this class.

A new paradigm for examining MOSFET failure modes

Abstract We describe the origin of the time dependence of various forms of defects under hot electron stress as arising from to the distribution of precursor energies. This has specific consequences on all failure modes which are caused by those particular types of defects. Using a simple model for hot carrier interface state generation and a percolation model for oxide breakdown, the roughly Weibull statistics thus generated are easily interpreted in terms of a few physical parameters. A multi-carrier model for interface state generation is also presented. The model provides an explanation for the observed transition of maximum stress voltage from Vg at maximum substrate current to Vg=Vd.