Leonard F. Register

Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices

An analytic model of the direct tunneling current in metal–oxide–semiconductor devices as a function of oxide field is presented. Accurate modeling of the low-field roll-off in the current results from proper modeling of the field dependencies of the sheet charge, electron impact frequency on the interface, and tunneling probability. To obtain the latter dependence, a modified WKB approximation is used.

Mechanism of stress-induced leakage current in MOS capacitors

Stress-induced leakage current (SILC) is examined both below and above the voltage at which the preexisting Fowler-Nordheim tunneling current dominates. Based on these results, it is argued that SILC is the result of inelastic rather than elastic trap-assisted tunneling. This clarification explains the well-known thickness dependence of the SILC at low fields that has identified it as a scaling limitation for nonvolatile memory tunnel oxide. It also explains a newly observed different thickness dependence at high fields and facilitates modeling of the electric field/voltage and trap density dependencies of the SILC.

Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device

We propose a new type of graphene-based transistor intended to allow lower voltage, lower power operation than possible with complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Increased energy efficiency is not only important for its own sake, but is also necessary to allow continued device scaling and the resulting increase in computational power in CMOS-like logic circuits. We describe the basic device structure and physics and predicted current-voltage characteristics. Advantages over CMOS in terms of lower voltage and power are discussed.

Effect of edge roughness on electronic transport in graphene nanoribbon channel metal-oxide-semiconductor field-effect transistors

Results of quantum mechanical simulations of the influence of edge disorder on transport in graphene nanoribbon metal-oxide-semiconductor field-effect transistors (MOSFETs) are reported. The addition of edge disorder significantly reduces ON-state currents and increases OFF-state currents, and introduces wide variability across devices. These effects decrease as ribbon widths increase and as edges become smoother. However, the band gap decreases with increasing width, thereby increasing the band-to-band tunneling mediated subthreshold leakage current even with perfect nanoribbons. These results suggest that without atomically precise edge control during fabrication, MOSFET performance gains through use of graphene will be difficult to achieve in complementary MOS applications.

Gate-tunable resonant tunneling in double bilayer graphene heterostructures.

We demonstrate gate-tunable resonant tunneling and negative differential resistance in the interlayer current-voltage characteristics of rotationally aligned double bilayer graphene heterostructures separated by hexagonal boron nitride (hBN) dielectric. An analysis of the heterostructure band alignment using individual layer densities, along with experimentally determined layer chemical potentials indicates that the resonance occurs when the energy bands of the two bilayer graphene are aligned. We discuss the tunneling resistance dependence on the interlayer hBN thickness, as well as the resonance width dependence on mobility and rotational alignment.

Graphene for CMOS and Beyond CMOS Applications

Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated with room temperature field-effect mobilities close to 10 000 cm2/Vs. But since graphene is a gapless semiconductor, these transistors have high off-state leakage and nonsaturating drive currents. This is problematic for digital logic, but is acceptable for analog device applications such as low-noise amplifiers and radio-frequency (RF)/millimeter-wave field-effect transistors (FETs). The remarkable transport physics of graphene due to its linear bandstructure have led to novel beyond CMOS logic devices as well, such as “pseudospin” devices.

Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1/spl times/10/sup 20/ cm/sup -3/ is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented.

Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability

Two-dimensional device simulations are used to explore the applications of bandgap engineering in improving device performance and scalability. Heterojunction pMOSFETs with strained SiGe in the source and/or drain have substantially suppressed short-channel effects, including field-induced barrier lowering in the devices with high-k gate dielectrics/spacers. Despite the source-side velocity overshoot, the drive currents in these devices are reduced due to the hetero-barriers in the channel. This drawback can be eliminated by the use of a thin Si or SiGe cap layer. Finally, a novel pMOSFET with a SiGe source/drain and a SiGe quantum well channel is proposed. It has reduced SCE and enhanced drive current.

Theory of channel hot-carrier degradation in MOSFETs

Abstract A critical but still poorly understood process in metal-oxide-semiconductor field-effect transistors (MOSFETs) is stress-induced changes in device threshold voltage, channel conductance, etc. which limit the operating lifetimes of the transistors. However, the degradation characteristics of deep-submicron MOSFETs, the widely demonstrated deuterium/hydrogen isotope effect, and the related results of scanning-tunneling microscopy (STM)-based depassivation experiments on silicon–vacuum interfaces are providing new insights into the degradation of MOSFETs via, at least, depassivation of the silicon-oxide interface. In this manuscript, we review the basic mechanisms of depassivation, suggest disorder-induced variations in the threshold energies for silicon–hydrogen/deuterium bond breaking as a possible explanation for observed sublinear time dependencies for degradation below t 0.5 , and show that excitation of the vibrational modes of the bonds could play a significant role in the continuing degradation of deep-submicron MOSFETs operated at low voltages.

Ballistic performance comparison of monolayer transition metal dichalcogenide MX2 (M = Mo, W; X = S, Se, Te) metal-oxide-semiconductor field effect transistors

We study the transport properties of monolayer MX2 (M = Mo, W; X = S, Se, Te) n- and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic non-equilibrium Greens function simulations with an atomistic tight-binding Hamiltonian with hopping potentials obtained from density functional theory. We discuss the subthreshold slope, drain-induced barrier lowering (DIBL), as well as gate-induced drain leakage (GIDL) for different monolayer MX2 MOSFETs. We also report the possibility of negative differential resistance behavior in the output characteristics of nanoscale monolayer MX2 MOSFETs.