Wjatscheslaw Galjan

12-bit hybrid C2C DAC based SAR ADC with floating voltage shield

A successive approximation ADC based on the C2C DAC architecture is introduced. The ADC designed in a 0.18µm CMOS 2 Poly 4 Metal process uses a hybrid capacitive DAC combining the best of the binary weighted capacitive array and the C2C array. C2C ladder based architectures are very attractive for implementation because of its small area, high speed and low power consumption. However a major drawback associated with this DAC is the presence of high parasitic bottom plate capacitances. A concept called the floating voltage shield (FVS) is introduced to reduce the effect of these parasitic capacitances and maximize the effective use of the C2C DAC features. The converter consists of the hybrid DAC, a two stage preamplifier followed by a dynamic latch, switch array and digital circuitry for switching and control. The ADC consumes a maximum power of 630µW at a peak conversion rate of approximately 2MS/s from a 1.8V supply voltage and 40MHz clock. Use of extremely simple and yet robust analog architectures for the comparator make the ADC operation less prone to process variation errors.

Highly sensitive biomedical amplifier with CMRR calibration and DC-offset compensation

To cover a wide range of biomedical applications, the presented instrumentational amplifier (INA) for acquisition of biomedical signals is adjustable regarding power consumption and noise. In addition, DC-offsets larger than ±500 mV resulting from electrochemical potentials of the electrodes can be compensated by applying a voltage to an additional input. To achieve a high common mode rejection ratio (CMRR) of more than 80 dB, a digitally controlled calibration circuitry has been integrated. The novel concept of calibrating the CMRR in the high resistive feedback loop of an opamp and the DC electrode potential suppression does not require any external components. The INA has been fabricated in a 350 nm CMOS technology.

A portable SoC-based ECG-system for 24h x 7d operating time

A portable battery powered 3-channel ECG-system is presented. This system can be operated up to 10 days by two standard AA batteries. It acquires 3 ECG signals with 16 bit resolution using a dedicated system on chip (SoC) with an embedded DSP for power efficient data handling. The digitized data are filtered with an 80th order FIR filter and stored on a compact flash (CF) card that can be read out using a standard PC operating system. Combining high performance analog parts for signal acquisition and a powerful DSP on a single chip opens up innovative possibilities in reduction of system size and power consumption.

A 130nm CMOS Programmable Operational Amplifier

In this work we present a programmable 1.2 V operational amplifier (OpAmp) realized in a standard 130 nm CMOS technology. The OpAmp is based on a 3 V rail-to-rail input/output topology. The experimental results show the feasibility of using higher voltage topologies in conjunction with multi-threshold (multi-Vth) process options for low voltage designs. The programming range extends from a low-noise to a low-power mode. In addition, a constant-gm stage has been added to the rail-to-rail input. In low-noise mode the OpAmp has a low input thermal noise voltage of 5.1 nV/¿Hz and in low-power mode a power consumption of only 203 ¿W. Over the whole programming range the OpAmp maintains unity-gain stability with its phase margin varying between 58° and 62°.

An Impedance Spectroscopy ASIC for Low-Frequency Characterization of Biological Samples

This paper describes the design and testing of an ASIC for impedance spectroscopy of biological samples at frequencies up to 40 kHz. The circuit is designed in the 350 nm AMS H35B4 technology and enables the measurement of impedances in the range of 10 k Ω up to 28 MΩ. The design features a digital oscillator and a current-to-voltage converter. The ASIC is used to monitor the growth of yeast cell cultures and porcine chondrocytes, in real-time, using a standard 384-well plate and copper electrodes.

A Configurable Integrated Circuit for Biomedical Signal Acquisition

A 10 channel CMOS integrated circuit (IC) for biomedical signal acquisition is presented. Each channel of the IC includes a programmable analog front-end (AFE) and a 20 bit analog-to-digital converter (ADC). An active DC-suppression circuitry allows to tolerate DC-offsets of up to ±1 V for a power supply voltage of 3.3 V. The AFE includes a common-mode rejection ratio (CMRR) calibration circuitry resulting in a CMRR of more than 80 dB. In low-noise mode the AFE achieves an input referred noise of less than 0.11 μV rms for EEG application (0.5-70 Hz) and the power consumption of the IC is less than 30 mW in low-power mode. An experimental USB-Stick for biomedical signal acquisition has been realized using the IC.