Wojciech Jalmuzna

FPGA-based implementation of a cavity field controller for FLASH and X-FEL

The subject of this paper is the design and construction of a new generation of superconducting cavity accelerator measurement and control system. The old system is based on a single digital signal processor (DSP). The new system uses a large programmable array circuit (FPGA) instead, with a multi-gigabit optical link. Both systems now work in parallel in the Free Electron Laser in Hamburg (FLASH). The differences between the systems are shown, based on the measurement results of the working machine. The major advantage of the new system is a bigger area of stability of the machine control loop.

Interfaces and communication protocols in ATCA-based LLRF control systems

Linear accelerators driving Free Electron Lasers (FELs), such as the Free Electron Laser in Hamburg (FLASH) or the X-ray Free Electron Laser (XFEL), require sophisticated Low Level Radio Frequency (LLRF) control systems. The controller of the LLRF system should stabilize the phase and amplitude of the field in accelerating modules below 0.02% of the amplitude and 0.01 degree for phase tolerances to produce an ultra stable electron beam that meets the required conditions for Self-Amplified Spontaneous Emission (SASE). Since the LLRF system for the XFEL must be in operation for the next 20 years, it should be reliable, reproducible and upgradeable. Having in mind all requirements of the LLRF control system, the Advanced Telecommunications Computing Architecture (ATCA) has been chosen to build a prototype of the LLRF system for the FLASH accelerator that is able to supervise 32 cavities of one RF station. The LLRF controller takes advantage of features offered by the ATCA standard. The LLRF system consists of a few ATCA carrier blades, Rear Transition Modules (RTM) and several Advanced Mezzanine Cards (AMCs) that provide all necessary digital and analog hardware components. The distributed hardware of the LLRF system requires a number of communication links that should provide different latencies, bandwidths and protocols. The paper presents the general view of the ATC A-based LLRF system, discusses requirements and proposes an application for various interfaces and protocols in the distributed LLRF control system.

FPGA-based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented.

Measurements of SIMCON 3.1 LLRF control signal processing quality for VUV Free Electron Laser FLASH

The paper describes development of a new version of photonic and electronic control and measurement system for FLASH Laser under development in DESY Hamburg accelerator laboratory. The system is called SIMCON 3.1. and is a developmental continuation of previous systems SIMCON 1.0, SIMCON 2.1 and SIMCON 3.0. It differs from the previous systems by considerably bigger resources: 10 fast analog input channels, bigger FPGA chip with two power PC - CPU units, two multi-gigabit optical links, GbE interface, booting possibility from flash memory card. The PCB is done in VME mechanical and electrical standard. It is designed for usage in tests for FLASH Laser development.

Distributed versus Centralized ATCA Computing Power

The RF Control for the European XFEL requires powerful data processing capability for many algorithms including feedback, calibration, diagnostics and low and high level applications needed for field control. While central processing architecture will be easier to manage and develop, it will also increase the requirements for the communication links connecting the boards. On the other hand, a distributed system improves performance and reliability but result in higher complexity. The trade-offs between the two architecture will be discussed and examples will be presented.

Implementation of adaptive feed-forward algorithm on embedded PowerPC405 processor for FLASH accelerator

This paper compares algorithms used for control of super-conducting cavities in the FLASH accelerator and laser in DESY Research Center (Hamburg, Germany), and describes features of the adaptive feed-forward algorithm. Described solution was implemented in the PowerPC 405 processor embedded in the Xilinx Virtex II Pro FPGA circuit.

Modular version of SIMCON, FPGA based, DSP integrated, LLRF control system for TESLA FEL part II: measurement of SIMCON 3.0 DSP daughterboard

The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the W-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layer, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACCl module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0. encouraged us to enter the design of SIMCON 3.1. possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0. is a modular solution, while SIMCON 3.1. will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one - after branching off in this version of the Simcon, will be continued.

Data transmission optical link for LLRF TESLA project part II: application for BER measurements

It may be predicted now, even assuming a very conservative approach, that the next generation of the Low Level RF control systems for future accelerators will use extensively such technologies like: very fast programmable circuits equipped with DSP, embedded PC and optical communication I/O functionalities, as well as multi-gigabit optical transmission of measurement data and control signals.

FPGA and optical network based LLRF distributed control system for TESLA-XFEL Linear Accelerator

The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control system for the TESLA-XFEL accelerator. The design of a system basing on the FPGA chips and multi-gigabit optical network was debated. The system design approach was fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of the, DSP enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. Initial parameters of the system model under the design are presented.

Data transmission optical link for LLRF TESLA project part I: hardware structure of OPT0 module

It may be predicted now, even assuming a very conservative approach, that the next generation of the Low Level RF control systems for future accelerators will use extensively such technologies like: very fast programmable circuits equipped with DSP, embedded PC and optical communication I/O functionalities, as well as multi-gigabit optical transmission of measurement data and control signals. The paper presents the idea and realization of a gigabit synchronous data distributor designed to work in the LLRF control system of TESLA technology based X-ray FEL. The design bases on a relatively simple and cheap FPGA chip Cyclone. Commercially available SERDES (serializer/deserializer) and optical transceiver chips were applied. The optoelectronic module is embedded on the main LLRF BMB (backbone mother board). The MB provides communication with the outside computer control system, programmable chip configuration, integration with other functional modules and power supply. The hardware implementation is here described and the used software for BER (bit-error-rate) testing of the multi-gigabit optical link. The measurement results are presented. The appendix contains a comparison between the available protocols of serial data transmission for FPGA technology. This paper is a partial contribution to the next version of the SIMCON system which is expected to be released this year. The SIMCON, ver 3.0 will contain 8 channels and multi-gigabit optical transmission capability. It will be a fully modular construction.