Wojciech Sulek

GF(q) LDPC decoder design for FPGA implementation

The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.

On the Overflow Problem in Finite Precision Turbo Decoding Message Passing

Much attention has been paid recently to the so-called layered decoding of LDPC codes, also known as turbo-decoding message passing (TDMP). The TDMP algorithm for decoding LDPC codes is known to possess some desirable features, such as fast convergence speed, reduced memory requirements and reduced implementation complexity in comparison with standard two-phase message passing algorithm. In this paper we analyze an important issue connected with hardware implementation of TDMP algorithm, namely the finite precision representation of messages influence on the decoding performance. Constrained dynamic range of the finite precision representation of messages entails overflow errors. We present an analysis revealing that in the subsequent decoding iterations, the subtraction of non-overflowed intrinsic message from overflowed extrinsic message is a source of errors that have substantial impact on the decoding results. The analysis is confirmed by simulation results showing significant performance loss. However this performance loss can be almost completely eliminated with a basic modifications in the messages computation algorithm. Effectiveness of the presented modifications is confirmed by simulation results obtained with hardware TDMP decoder implementation that has been developed.

Transmission over UWB Channels with OFDM System using LDPC Coding

Hostile wireless environment requires use of sophisticated signal processing methods. The paper concerns on Ultra Wideband (UWB) transmission over Personal Area Networks (PAN) including MB-OFDM specification of physical layer. In presented work the transmission system with OFDM modulation was connected with LDPC encoder/decoder. Additionally the frame and bit error rate (FER and BER) of the system was decreased using results from the LDPC decoder in a kind of turbo equalization algorithm for better channel estimation. Computational block using evolutionary strategy, from genetic algorithms family, was also used in presented system. It was placed after SPA (Sum-Product Algorithm) decoder and is conditionally turned on in the decoding process. The result is increased effectiveness of the whole system, especially lower FER. The system was tested with two types of LDPC codes, depending on type of parity check matrices: randomly generated and constructed deterministically, optimized for practical decoder architecture implemented in the FPGA device.

Code construction algorithm for architecture aware LDPC codes with low-error-floor

The common approach for the design of an error correction system is first to construct a code and then to define the hardware structure of the encoder and decoder. However, in the case of LDPC codes (low-density parity-check) such a constructed code is generally not well suited for a hardware implementation. It has been recognized that the code construction and hardware design must be considered jointly to facilitate LDPC decoder and encoder implementation. In this paper, an efficient decoder structure for regular and irregular LDPC codes, based on TDMP (turbo-decoding message passing) scheme is designed first. The decoder has been implemented and verified in an FPGA device. Constraints for the parity check matrix of a code to be suitable for the decoder architecture are defined. Then an algorithm for LDPC parity check matrix construction subject to these constraints is presented. The algorithm aims at improving performance of the code in the low SNR region by employing irregular codes as well as in high SNR region by reducing the number of small Stopping Sets and Trapping Sets in the Tanner graph of the code making use of a computer search technique.

Seed graph expansion for construction of structured LDPC codes

A lot of works concerning LDPC codes construction has been published so far. However, it is well known that efficient partially parallel hardware decoder architectures are allowed only for LDPC codes with blockwise partitioned structure of the parity check matrix, called structured LDPC codes. Two main steps in the structured LDPC code parity check matrix construction are the seed matrix (seed graph) construction and expansion of the seed matrix (seed graph). In this paper we present a flexible method for seed matrix expansion by computer search technique for the optimum shift values of the circulant submatrices. The proposed algorithm aims at reducing existence in the code graph of small cycles with low external connectivity that constitute structures known as Stopping Sets and Trapping Sets that are harmful to the code performance, especially in the high SNR region. The algorithm can be used for regular or irregular code construction of any block length and code rate.

Nonbinary Quasi-Regular QC-LDPC Codes Derived From Cycle Codes

Nonbinary ultra sparse codes, particularly regular cycle codes, are known to approach Shannon-limit performance as the Galois field GF(q) order is sufficiently large. Good cycle codes can result from a class of algebraically defined graphs called cages. Meanwhile, when smaller q is desirable, the cycle codes are outperformed by quasi-regular codes. In this letter, we propose a code construction method that takes a cage as a starting point and then progressively inserts a few additional edges into the graph. The edge insertion is terminated as soon as the code performance stops improving. Our simulation results show that the obtained quasi-regular codes outperform cyclic codes for fields up to GF(64) and its performance is slightly better than the quasi-regular improved-Progressive Edge Growth-based codes. The proposed algorithm preserves the block-circulant structure of the initial cage-based graph; therefore, it can be used for structured or quasi-cyclic codes design.

OFDM Transmission with Non-binary LDPC Coding in Wireless Networks

High-quality information exchange between upper layers of the communication network (e.g. TCP, IP layers) requires reliable connection of communicating devices on the physical layer. Any non-corrected errors at this level force the upper layers to perform proper action to recover transmitted information. It reduces data throughput and increases delay to unacceptable level for some services. Among physical media, wireless one is the most hostile environment, due to its unpredictable behavior. In that case, OFDM (Orthogonal Frequency Division Multiplex) modulation and LDPC (Low Density Parity Check) error correction codes appear the best choice to provide high transmission quality on the physical layer. This paper presents the results of the authors’ simulation of a LDPC-coded OFDM system with particular emphasis on codes over high order Galois fields (non-binary) which are not commercialized yet.

Idle time reduction in TDMP implementation of LDPC decoder

This article concerns the hardware iterative decoder for a subclass of LDPC (Low-Density Parity-Check) codes that are implementation oriented. They are known as Architecture Aware LDPC (AA-LDPC). The decoder has been implemented in a form of parameterizable VHDL description. To achieve high clock frequency of the decoder hardware implementation, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a heuristic algorithm for parity check matrix optimization to minimize the total number of required idle cycles and hence maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties, however the decoder throughput can be significantly increased.

Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation

Most of the recently proposed hardware realizations for non-binary low-density parity-check decoders are ASIC oriented as they employ multiplierless computation units. In this article, we present a different decoder design approach that is specifically intended for an FPGA implementation. We reformulate the mixed-domain FFT-BP decoding algorithm and develop a decoder architecture that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA, thus making use of all the types of FPGA resources. Then, the throughput limit achievable in a single FPGA by the proposed decoder is significantly increased. We also consider another important optimization of the decoder implementation, mainly an efficient realization of the permutation units and an approximated evaluation of the nonlinear functions of messages. Another motivation is to make the decoder easily scalable for FPGA devices of different sizes. To achieve this goal, the configurable semi-parallel decoder architecture is applied operating for the structured subclass of codes.

Subchannel ordering scheme for LDPC-coded OFDM transmission over selective channels

OFDM modulation seems to be a good choice to deal with highly distorted transmission channels, and LDPC error correction codes allow the system performance to get close to the Shannon capacity. Performance improvement of the LDPC-coded OFDM system can be accomplished by use of irregular binary LDPC codes along with an appropriate match between the bits of the codeword and the OFDM subchannels. Non-binary LDPC codes over high order finite fields GF(q) are an additional booster in case of short to moderate codeword lengths. In this paper, a simple practical method of the subchannel ordering for OFDM modulation with non-binary LDPC codes is proposed. The method exploits some special structural properties of the LDPC code parity check matrix generated based on the PEG (Progressive-Edge-Growth) algorithm. A noticeable improvement was achieved for regular codes when the column weights of the parity check matrix is equal to 2.