Dariusz Kania

Area and speed oriented synthesis of FSMs for PAL-based CPLDs

New two-step methods of FSMs synthesis for PAL-based CPLDs are presented in the paper. The methods strive to find the optimum fit for a FSM to the structure of CPLD and aim at area and speed optimization. The first step for both methods is original state assignment that includes: techniques of two-level minimization, the limited number of terms contained in the cell and elements of adjusting to the logic optimization. The second step in the method oriented toward area minimization is PAL-oriented multi-level optimization, which is a search for implicants that can be shared by several functions. The second step in the method oriented toward speed maximization is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block.

Decomposition-based logic synthesis for PAL-based CPLDs

Decomposition-based logic synthesis for PAL-based CPLDs The paper presents one concept of decomposition methods dedicated to PAL-based CPLDs. The proposed approach is an alternative to the classical one, which is based on two-level minimization of separate single-output functions. The key idea of the algorithm is to search for free blocks that could be implemented in PAL-based logic blocks containing a limited number of product terms. In order to better exploit the number of product terms, two-stage decomposition and BDD-based decomposition are to be used. In BDD-based decomposition methods, functions are represented by Reduced Ordered Binary Decision Diagrams (ROBDDs). The results of experiments prove that the proposed solution is more effective, in terms of the usage of programmable device resources, compared with the classical ones.

Logic synthesis for PAL-based CPLD-s based on two-stage decomposition

A PAL-based (PAL - Programmable Array Logic) logic block is the core of a great majority of contemporary CPLD (Complex Programmable Logic Device) circuits. The purpose of the paper is to present a novel method of two-stage decomposition dedicated for PAL-based CPLD-s. The key point of the algorithm lies in sequential search for a decomposition providing feasibility of implementation of the free block in one PAL-based logic block containing a limited number of product terms. The proposed method is an alternative to the classical approach, based on two-level minimisation of separate single-output functions. An original method of determining the row multiplicity of the partition matrix is presented. For this purpose a new concept of graph is proposed - the Row Incompatibility and Complement Graph. An appropriate algorithm of the Row Incompatibility and Complement Graph colouring is presented. On the basis of row multiplicity evaluated for individual partitionings, the partitioning which provides minimisation of the bound block is chosen. Results of the experiments, which are also presented, prove that the proposed method leads to significant reduction of chip area in relation to the classical approach, especially for CPLD structures, that consist of PAL-based blocks containing 2^i (a power of 2) product terms. The proposed method was also compared with decomposition algorithms presented in another works. The results lead to a conclusion, that the proposed two-stage PAL decomposition is especially attractive with respect to the number of logic levels obtained.

Decomposition-based synthesis and its application in PAL-oriented technology mapping

Most CPLD architectures include PAL based logic blocks containing a limited number of terms connected to the individual output macrocell. These blocks often contain three-state output buffers. Appropriate partition of whole devices into suitable logic block is one of the basic problems of the synthesis process. A method for logic synthesis based on decomposition for a PAL based logic block with three-state output buffers is presented. Decomposition is the main element and first step of the synthesis process. Fundamental to PAL oriented decomposition is the Curtis theory. The constrained decomposition algorithm is based on a proposed PAL oriented graph colouring. Additionally, the method of two-level logic synthesis, which makes use of three-state output buffers, is used for implemented free and bound logic blocks. Experimental results are compared to previously published methods and firmware tools are given to show the efficiency of this approach.

State assignment for PAL-based CPLDs

In the paper, the state assignment methods of the finite state machines for PAL-based structures are presented. A main feature of the PAL-cell is a limited number of product terms (k-AND-gates) that are connected to a single sum (OR-gate). Function, which is the sum of p-implicants, when p/spl ne/k, does not take full advantage of the cell. When p>k, implementation is multi-cell (so multi-level). The main idea of solving this problem is to count the number of product terms during the process of state assignment. First algorithm leads to automata which take advantage of the number of PAL-cell terms. Second approach is dedicated to state assignment of fast automata. Methods based on primary and secondary merging conditions are presented. In one of the most basic states of the logic synthesis of sequential devices, the elements referring to restrictions of PAL-based CPLDs are taken into account.

A technology mapping algorithm for PAL-based devices using multi-output function graphs

The objective of the technology mapping method presented in this paper is to cover a multiple-output function by a minimal number of PAL (programmable array logic) based logic blocks included in CPLDs (complex programmable logic devices). According to this method, product terms included in a logic block can be shared by several functions. The developed algorithms, implemented within the PALDec system, have been used for partitioning the benchmark circuits due to implementation by means of the PAL-based logic blocks with the restricted number of terms. The results are compared to the classical technology mapping method and synthesis of benchmarks executed by means of MACHXL and MAX+PLUS II software.

Logic synthesis based on decomposition for CPLDs

The paper presents a decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, which leads to the minimization of area in an implemented circuit and the reduction of used logic blocks in a programmable structure, is the aim of the proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc.) is oriented for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The proposed decomposition method is an extension of the classical approach, commonly thought to be adequately efficient. Experiments carried out on typical benchmarks show significant area reduction.

Synthesis of finite state machines for CPLDs

Synthesis of finite state machines for CPLDs The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.

Logic synthesis of multi-output functions for PAL-based CPLDs

In this paper multi-level synthesis for PAL-based CPLDs is presented. The essence of the method is to search for multi-output implicants that can be shared by several functions. This approach presents a unique form for illustrating a minimized form of a multi-output Boolean function. The presented method, implemented within the PALDec system, is based on the analysis of graph nodes that represent states of a digital circuit outputs. The results of synthesis for benchmarks are compared to the classical technology mapping method.

A novel method of two-stage decomposition dedicated for PAL-based CPLDs

A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a novel method of two-stage PAL decomposition. The idea of the method consist in sequential search for a decomposition providing feasibility of implementation of the free block in a PAL-based logic block containing a limited number of product terms. The proposed approach is an alternative to the classical method based on two-level minimization of separate single-output functions. Results of experiments, which are also presented, prove that the proposed algorithm leads to significant reduction of chip area in relation to the classical method, especially for CPLD structures consisting of PAL-based logic blocks containing 2/sup i/ (a power of 2) product terms.