Wolfram Lautenschlaeger
Alcatel-Lucent
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Wolfram Lautenschlaeger.
Proceedings of SPIE, the International Society for Optical Engineering | 2006
Helen C. Leligou; Gert Eilenberger; Lars Dembeck; Wolfram Lautenschlaeger; Stephan Bunse; A. Stavdas; John D. Angelopoulos; Christina Tanya Politi
In spite of its long term promise, all-optical switching is still plagued by high cost, low efficiency when handling bursty data traffic, immature management and protection and poor output port contention resolution leading to heavy loss. Given the current situation, hybrid approaches that keep the best features of optics, reverting to the electrical plane when expedient, constitute sensible interim steps that can offer cost-effective solutions along the road to an eventual all-optical core. Two such approaches developed in the framework of the European IP project NOBEL are presented in this work. The first is a quite mature solution that extends present day concepts to achieve multiplexing gain while keeping all the management and restoration benefits of SDH. The other mimics early LANs in executing a distributed switching via its electrical control plane using two-way reservations, thus restricting its applicability to smaller domains. Combining the two leads to a system fulfilling most of todays requirements for Tb/s core networks.
field-programmable logic and applications | 2008
George Kornaros; Wolfram Lautenschlaeger; Matthias Sund; Helen-Catherine Leligou
This paper describes the efficient implementation of a Frame Aggregation Unit that gathers Ethernet packets in G.709 containers. This design has the capacity to handle 10 Gbps links, to perform classification based on 24-byte header, and includes a highly pipelined Queue Manager to cope with the considered rates while a specific scheduler controls the quality of service per core network flow. The obtained results as regards area and performance for an actual working FPGA Virtex-4 implementation are provided while the reported complexity is equivalent to 11.4 Mgates at 180 MHz.
Archive | 2004
Wolfram Lautenschlaeger
Archive | 2008
Wolfram Lautenschlaeger
Archive | 2006
Wolfram Lautenschlaeger
Archive | 2010
Wolfram Lautenschlaeger
Archive | 2013
Wolfram Lautenschlaeger
Archive | 2010
Wolfram Lautenschlaeger
Archive | 2006
Wolfram Lautenschlaeger
Archive | 2005
Wolfram Lautenschlaeger