Wolfram Putzke-Röming

Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture

Despite recent advances in FPGA, GPU, and general purpose processor technologies, the challenges posed by real-time digital image processing at high resolutions cannot be fully overcome due to insufficient processing capability, inadequate data transport and control mechanisms, and often prohibitively high costs. To address these issues, we proposed a two-phase solution for a real-time film grain noise reduction application. The first phase is based on a state-of-the-art FPGA platform used as a reference design. The second phase is based on a novel heterogeneous reconfigurable computing platform that offers flexibility not available from other computing paradigms. This paper introduces the heterogeneous platform and briefly reviews our previous work with the application in question, as well as its implementation on the FPGA demonstration board during the first phase. Then we present a decomposition of the application, which allows an efficient mapping to the new heterogeneous computing platform through the use of its diverse reconfigurable computing units and run-time reconfiguration.

A flexible message passing mechanism for objective VHDL

When defining an object-oriented extension to VHDL, the necessary message passing is one of the most complex issues and has a large impact on the whole language. This paper identifies the requirements for message passing suited to model hardware and classifies different approaches. To allow abstract communication and reuse of protocols on system level, a new, flexible message passing mechanism proposed for Objective VHDL is introduced.

Object-Oriented Specification and Design of Embedded Hard Real-Time Systems

The approach presented in this paper is a contribution to combine well established methodologies in software engineering, namely object-orientation, with novel co-simulation techniques for real-time HW/SW system simulation, and new synthesis techniques based on the HW-semantics of object-oriented HW-specifications. The result is a consistent object-oriented design process for safety critical hard real-time embedded systems. Its objective is to decrease the design time of such systems by improving the re-usability, enabling concurrent HW/SW co-design and avoiding unnecessary iteration loops to meet timing constraints. The paper presents a motivation for and a survey of the methodology as well as a brief introduction into the different phases of the process, in particular simulation and synthesis. The concepts are illustrated by a consistent example taken from an established system level benchmark.

Application-specific memory performance of a heterogeneous reconfigurable architecture

Heterogeneous reconfigurable processing architectures are often limited by the speed at which they can access data in external memory. Such architectures are designed for flexibility to support a broad range of target applications, including advanced algorithms with significant processing and data requirements. Clearly, strong performance of applications in this category is an extremely relevant metric for demonstrating the full performance potential of heterogeneous computing platforms. One such example, a film grain noise reduction application for high-definition video, which is composed of multiple image processing tasks, requires enormous data rates due to its large input image size and real-time processing constraints. This application is especially representative of highly parallel, heterogeneous, data-intensive programs that can properly exploit the advantages offered by computing platforms with multiple heterogeneous reconfigurable processing elements. To accomplish this task and meet the above requirements, a bandwidth-optimized external memory controller has been designed for use with a heterogeneous reconfigurable architecture and its NoC interconnect. With the help of the application described above, this paper evaluates the proposed architecture in two forms: (1) with a basic memory controller IP and (2) with the advanced memory controller design. The results illustrate the full potential of the computing platform as well as the power of heterogeneous reconfigurable computing combined with high-speed access to large external memories.

Data type analysis for hardware synthesis from object-oriented models

Object-oriented modeling of hardware promises to help deal with design complexity through higher abstraction and better support for reuse. Whereas simulation of such models is rather easy to achieve, synthesis turns out to require the application of quite sophisticated techniques. In this paper, we devise a solution of the foremost problem, optimized synthesis of object-oriented data types. The outlined algorithms have been implemented for an object-oriented dialect of VHDL and may also contribute, possibly in a co-design context, to synthesis from languages such as C++ or Java. We explain our synthesis methods and show their impact with the example of a microprocessor model.

Modeling communication with Objective VHDL

Objective VHDL was developed to utilize the object-oriented paradigm to the hardware design process. In order to facilitate flexible modeling of communication among (entity) objects appropriate to the specific context, no message passing mechanism has been integrated into the language. Based on earlier ideas related to message passing with Objective VHDL the paper demonstrates the design and implementation of a complete communication mechanism. As an example a non blocking handshake protocol is chosen. Special emphasis has been given to an abstract user-interface and good reusability of the communication mechanism.

Synthesis Oriented Communication Design for Structural Hardware Objects

An object-oriented HDL has to provide an appropriate communication concept for communication between objects. Unfortunately, exactly the communication concept can be identified often as a critical issue in several existing proposals for object-oriented HDLs. In this paper we present requirements for such a communication concept and exemplary define a new object-and synthesis-oriented communication model for Objective VHDL.