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Dive into the research topics where Won-Eui Hong is active.

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Featured researches published by Won-Eui Hong.


Applied Physics Letters | 2010

Supergrains produced by lateral growth using Joule-heating induced crystallization without artificial control

Won-Eui Hong; Jangkyun Chung; Dong Hyun Kim; Seungho Park; Jae-Sang Ro

In Joule-heating induced crystallization, phase transformation can occur through solid-to-solid or liquid-to-solid phases, according to the input conditions of the pulsed power. It was observed that during a Joule-heating period of several tens of microseconds, randomly nucleated liquid seeds followed by rapid solidification in an amorphous matrix play an important role, especially for liquid-to-solid transformation. Meanwhile, under high-power input processing conditions, supergrains of greater than 5 μm in size were produced by lateral growth from the initial seeds without artificial control.


Journal of Applied Physics | 2013

Kinetics of solid phase crystallization of amorphous silicon analyzed by Raman spectroscopy

Won-Eui Hong; Jae-Sang Ro

Solid phase crystallization (SPC) of amorphous silicon films grown by low pressure chemical vapor deposition was conducted using a tube furnace in nitrogen ambient at temperatures ranging from 560 °C to 1000 °C. The transformed crystalline fraction shows typical sigmoidal curves as a function of annealing time using Raman analysis adopted in this work. Arrhenius plot of the measured incubation time does not fit to the straight line since SPC kinetics has strong temperature dependence and since the heating rate is slow when using a conventional heating method. The grain size decreases as the annealing temperature increases. It, however, is not sensitive to the annealing temperature beyond 800 °C, since SPC kinetics is complete during the period of heating-up according to Raman spectroscopy. It was observed that doping of impurity atoms affect the crystallization kinetics.


SID Symposium Digest of Technical Papers | 2011

10.4L: Late‐News Paper: Joule Heating Induced Lift‐off Technology for Large Area Flexible AMOLED Displays

Moo-Voon Ko; Choong-Youl Im; Il-Jeong Lee; Jong-hyuk Lee; Sungchul Kim; Won-Eui Hong; Jae-Sang Ro

For large area flexible active matrix organic light emitting diode AMOLED display, we have developed a novel lift off method. This novel technology named as Joule heating induced lift-off JILO uses pulsed electric field for debonding of plastic and the substrate glass. We fabricated the low temperature poly silicon LTPS thin film transistors TFTs on the plastic film. Applying JILO, we can successfully develop flexible TFTs with no damage on transistor performance


SID Symposium Digest of Technical Papers | 2006

28.4L: Late‐News Paper: Millisecond Crystallization of Amorphous Silicon Film using Joule Heating

Jae-Sang Ro; Won-Eui Hong

A novel crystallization technology for amorphous silicon film using Joule heating was attempted in this study. An electric field is applied to a conductive layer, underneath, or, above, a silicon film to induce Joule heating to generate intense heat in order to carry out crystallization of amorphous silicon. Power density was more than 1,000 watt/cm2 and heating rate was higher than 100,000°C/sec under typical conditions of the experiments. Crystallization was accomplished uniformly throughout the sample within a few tens of milliseconds of the heating demonstrating a possibility of a new crystallization route of amorphous silicon films.


Japanese Journal of Applied Physics | 2006

Joule-Heating-Induced Annealing by Applying Electric Field Directly to Intrinsic Silicon Film

Jae-Sang Ro; Won-Eui Hong

A method of annealing silicon thin films by direct Joule heating of an intrinsic silicon film is suggested. Although amorphous silicon (a-Si) is an insulator, the electrical resistance of a-Si films can be lowered to a value that enables Joule heating by preheating a glass substrate, on which an insulation layer and an a-Si film are subsequently formed, for a certain period of time. As the preheating time is increased to the first threshold time, the electrical resistance of the thin film is lowered to a certain value, thereby causing electrical resistance to become saturated. Beyond a certain point, the electrical resistance of the thin film ceases to change even though the preheating time is continued. This continues up to the point when preheating time reaches the second threshold time, where the electrical resistance of the thin film decreases. After the second threshold time, when the electrical resistance of the film approaches a value below 50 kΩ and when an electric field is applied to Si films, Joule heating causes the temperature of the silicon film to increase rapidly. By this process the rapid thermal annealing of silicon thin films or other semiconductor films can be accomplished.


Journal of Applied Physics | 2005

Activation and deactivation in heavily boron-doped silicon using ultra-low-energy ion implantation

Won-Eui Hong; Jae-Sang Ro

A shallow p+∕n junction was formed using an ultra-low-energy implanter. Activation annealing exhibited both solid phase epitaxy, in which the sheet resistance dropped rapidly, and reverse annealing. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of the postannealing time and temperature following the rapid thermal annealing treatments. We found that the deactivation kinetics were divided into two regions. In the first region the rate of deactivation increased exponentially with the annealing temperature of up to 850°C. In the second region it decreased as the annealing temperature exceeded 850°C. We believe that the first region is kinetically limited while the second one is thermodynamically limited. In addition, we observed “transient enhanced deactivation,” an anomalous increase in the sheet resistance during the early annealing stage where the the temperatures were higher than 800°C. The activation energy for transient enhanced deactivation was mea...


Journal of the Korean institute of surface engineering | 2010

Behavior of Solid Phase Crystallization of Amorphous Silicon Films at High Temperatures according to Raman Spectroscopy

Won-Eui Hong; Jae-Sang Ro

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.


Journal of the Korean institute of surface engineering | 2008

Solid Phase Crystallization Kinetics of Amorphous Silicon at High Temperatures

Won-Eui Hong; Bo-Kyung Kim; Jae-Sang Ro

Solid phase crystallization (SPC) of amorphous silicon is usually conducted at around 600°C since it is used In the application of flat panel display using thermally susceptible glass substrate. In this study we conducted SPC experiments at temperatures higher than 600°C using silicon wafers. Crystallization rate becomes dramatically rapid at higher temperatures since SPC kinetics is controlled by nucleation with high value of activation energy. We report SPC kinetics of high temperatures compared to that of low temperatures.


international microprocesses and nanotechnology conference | 2001

Ion beam lithography using membrane masks

Yunhee Kim; Won-Eui Hong; Hyun-Jong Woo; Hoon-Sung Choi; Kang-Pil Kim; S. Lee

In this paper, we demonstrate both by simulation and experiment that, by using membrane masks, sub-100 nm patterns can be generated with practical mask to wafer distances (∼10 μm). We discuss the straggling problem and membrane mask preparation, and present ion beam lithography results.


Thin Solid Films | 2007

Millisecond crystallization of amorphous silicon films by joule-heating induced crystallization using a conductive layer

Won-Eui Hong; Jae-Sang Ro

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