Won-Tae Lee

A Lightweight Algorithm for Probability-Based Spectrum Decision Scheme in Multiple Channels Cognitive Radio Networks

Compare with the sensing-based spectrum decision scheme, the probability-based spectrum decision scheme has been shown to yield a shorter queuing delay time in Cognitive Radio (CR) system that consists of many Primary Users (PUs) and Secondary Users (SUs). However, the former scheme had cumbersome algorithms and slowly converging speed. In this paper, by introducing Lagrange function, we propose a lightweight algorithm with the computational effort O(N) to define the optimal distribution probability vector. Numerical results demonstrate a high degree of accuracy for the derived expressions.

SoC design and implementation for high reliable narrow-band power-line communications

This paper describes a dual-mode type architecture for a high reliable narrow-band power-line communication (PLC) modem, and its design and implementation of a system-on-a-chip (SoC). The designed architecture is based on a chirp modulation technique for the purpose of overcoming time variations of power-line channel environments in the narrow-bandwidth of the frequency range of 95 - 148.5 kHz. The designed modem is fabricated utilizing a mixed 0.18 mum CMOS technology. Especially, according to the power-line channel environments the data transmission rate can be selectively changed into 2.5 kbps and 480 bps. The total hardware complexity of the implemented chip is about 50,000 gates, the power consumption is about 26 mW, and the operating frequency is up to 5.12 MHz.

A Common Signaling Mechanism for Coexistence between High-speed Power Line Communication

AbstractIn the field of high-speed power line communications, there are three major standards; ISO/IEC 12139–1, IEEE 1901–2010, and ITU-T G.99xx. However, they are not interoperable because of having their own physical and MAC layer specification. Actually, they cannot even avoid interfering with each other because they are using the same frequency band of 1 ∼ 30 MHz. In this paper, a common signaling mechanism is suggested which uses multi-carrier partitioning and carrier sensing, so that all standards can be coexisted by sharing time resource. The suggested mechanism has been compared with the ISP protocol which is included in IEEE and ITU-T standard for coexistence.

SoC Design of a Dual-Mode Transceiver for Power-Line Telecommunications

In this paper, the design of a dual-mode transceiver for a power-line telecommunications (D-PLT) is described. We investigate on designing a system architecture of the D-PLT, adopting an efficient modulation technique against power-line channel and supporting a high reliability, which is well suited for the CENELEC B, C, and D bands roughly from 90 to 150 kHz. The proposed D-PLT is eventually integrated to a system-on-a-chip (SoC), synthesizing all of a baseband transceiver, a channel forward error correction (FEC) module, a micro-controller unit (MCU) to access communication protocols, and analog front end circuits, i.e., a pre-amplifier, a gain-amplifier, a digital-to-analog converter (DAC), a comparator, as well as external interfaces to communicate with application layer. The designed D-PLT is fabricated utilizing a mixed 0.18 um CMOS technology and it is required a total area of about 9,576 mm^2 consuming about 148 mW at the maximum data rates of 2.5 kbps.

A finite field inversion circuit for high-speed communications

To design a finite field inversion circuit for high-speed communications, we study two variations - that is, square-first and multiply-first type operations - for the repetition-operation of the numerical formula, AB/sub 2/. From these two variations, we propose m-bit parallel semi-systolic architectures for GF(2/sup m/) inversion. When we compared performance of them with those of different inversion architectures based on a normal power-sum operation, based on small grain of special power-sum operation, and based on a Euclidean algorithm, performance of the proposed one, which is based on small grain of special power-sum operation, is the best for the purpose of high-speed applications. When we implement a simplified 8-bit parallel semi-systolic architecture for square-first inversion circuit over GF(2/sup m/) by using 0.25 /spl mu/m CMOS library, it has 2495 equivalent logic-gates, 1848 1-bit latches, and the latency is 56 and the clock-rate is up to 580 MHz at 100% throughput.