Bertan Bakkaloglu

A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends

As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However, the supply voltage and power consumption of the RF front-end and analog sections do not scale in a similar fashion. In fact, in many state-of-the-art communication transceivers, RF and analog sections can consume more energy compared to the digital part. In this paper, first, a system level energy model for all the components in the RF and analog front-end is presented. Next, the RF and analog front-end energy consumption and communication quality of three representative systems are analyzed: a single user point-to-point wireless data communication system, a multi-user code division multiple access (CDMA)-based system and a receive-only video distribution system. For the single user system, the effect of occupied signal bandwidth, peak-to-average ratio (PAR), symbol rate, constellation size, and pulse-shaping filter roll-off factor is analyzed; for the CDMA-based multi-user system, the effect of the number of users in the cell and multiple access interference (MAI) along with the PAR and filter roll-off factor is studied; for the receive-only system, the effect of 1/f noise for direct-conversion receiver and the effect of IF frequency for low-IF architecture on the RF front-end power consumption is analyzed. For a given communication quality specification, it is shown that the energy consumption of a wireless communication front-end can be scaled down by adjusting parameters such as the pulse shaping filter roll-off factor, constellation size, symbol rate, number of users in the cell, and signal center frequency

A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.

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A combined linear and Δ-modulated switched-mode PA supply modulator for polar transmitters is designed in a 0.25μm CMOS process. The modulator follows the input envelope and achieves 20dB output DR, a maximum efficiency of 75.5%, and 75dB SNDR for envelope signals up to 4MHz occupied RF BW. For a 1625kb/s 8PSK RF input at 900MHz, polar modulation of a GSM-900 PA provides 10dB ACPR improvement.

m SiGe Process

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.

Combined Linear and Δ-Modulated Switched-Mode PA Supply Modulator for Polar Transmitters

In this paper, we propose a new architecture for a closed-loop controlled antenna tuning unit (ATU) system (only transmitting path is shown). In contrast to previous work, no analog-to-digital converters (ADCs) are used. Using the ATU, the narrow instantaneous bandwidth of an electrically small antenna (ESA) is automatically tuned over a much wider frequency range by the ATU. This matching scheme ensures that the narrowband antenna is automatically matched to any desired frequency under all environmental conditions using circuits with practical component values and tolerances. It is imperative that the entire tuning process be completed rapidly using efficient algorithms and fast hardware, and for these algorithms and hardware to consume as little power as possible.

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

A 6 GHz Type-I fractional-N PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization noise by more than 25 dB. The worst case near-integer in-band spur is measured at -61 dBc and the integrated RMS phase error is - 42 dBc. The measured in-band phase noise at 300 kHz offset from the 6.12 GHz carrier is -102 dBc/Hz and out-of-band phase noise at 3 MHz offset is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.01 ppm and a frequency step of 60 MHz is less than 11 ? s. The synthesizer is fabricated in a 0.18 ?m CMOS technology with 6 metal layers and consumes 26 mA from a 1.8 V power supply.

Automatic antenna tuning unit for software-defined and cognitive radio

A fully integrated 0.18mum SiGe synchronous buck DC/DC converter with an on-chip LC output filter supporting a maximum output current of 200mA and efficiency of 64% is presented. The converter utilizes a 10mum-thick electroplated copper layer for integrated inductors and gate capacitors. High switching frequency of 45MHz, multi-phase interleaved operation, and fast hysteretic control reduces the filter inductor and capacitor sizes by two orders of magnitude enabling a fully integrated converter

A 1 MHz Bandwidth, 6 GHz 0.18

A combined class-AB and switch-mode regulator based supply modulator with a master-slave architecture achieving wide bandwidth and low ripple is presented. Low frequency content of the envelope waveform is provided by a synchronous-rectifier based switch-mode power supply while high frequency content is provided by a rail-to-rail class-AB amplifier. A wide range, low loss output current sensing circuit is used at the class-AB amplifier output, canceling the ripple due to switch-mode power supply and extending overall modulator bandwidth. The proposed regulator is designed and fabricated on a 0.35 mum CMOS process. The combined regulator achieves a maximum efficiency of 82% and an IMD3 of 65 dBc at 10 MHz for 16 dBm output power. The regulator achieves a frequency range up to 10 MHz with less than 0.2% envelope tracking error, making this PA regulator suitable for CDMA applications.

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Wideband low-noise SigmaDelta fractional-N synthesizers pose several design challenges due to the nonlinear time-varying nature of synthesizer building blocks such as phase frequency detectors (PFDs), charge pump, and frequency dividers. Loop nonlinearities can increase close-in phase noise and enhance spurious tones due to intermodulation of high-frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper a closed-loop nonlinear simulation model for fractional-N synthesizers is presented. Inherent nonuniform sampling of the PFD is modeled through an event-driven dual-iteration-based technique. The proposed technique generates a vector of piecewise linear time-voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage. This method also lends itself to modeling of cyclostationary thermal and flicker noise generated by time-varying charge-pump current pulses. A flexible third-order SigmaDelta modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-mum CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8-dB accuracy, and spur frequency offsets with lower than 400-Hz accuracy with several programmable nonidealities enabled

m CMOS Type-I

Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise floor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is -105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply.