Woo-Seop Kim

55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate length of 55 nm. Compared to the previous reports, proposed cell transistor shows twice longer retention time even though the gate length shrinks to the half of them. By TCAD analysis, we have confirmed that the improvements are attributed to the superiority of the proposed device structure.

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

We describe a DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies. It utilizes simultaneous bidirectional (SBD) signaling in a daisy-chained (repeated), point-to-point configuration to enable high performance scalable memory subsystems; and also provides direct attach capability for DRAMs to memory controllers or other logic devices. Source-synchronous strobes are used for data capture, minimizing strobe-to-data jitter. A low-jitter differential clock retimes the data at each DRAM on a per DIMM basis preventing jitter from accumulating in repeated data. The phase of this clock is adjusted on each DRAM to minimize the latency of the repeaters. 80 mW of total power is dissipated per DRAM I/O at 3.6 Gb/s. We present results from a system using both memory controller and DRAM repeater test chips.

A control network architecture based on EIA-709.1 protocol for power line data communications

This paper presents an EIA-709.1 protocol architecture that can alleviate the burden of data communications in the Neuron chip. The proposed protocol is implemented with partly hardware and partly software. The physical layer and the MAC layer of the EIA-709.1 protocol are implemented with hardware. The upper link layer of the EIA-709.1 protocol is implemented with software. We verified the commercial feasibility of the proposed system through the power line tests with the existing LonWorks network. As a result, it is concluded that the proposed architecture provides flexibility and cost benefit for the system implementations.

BER Simulator Development for Link Compliance Analysis

This paper is related to developing new Bit Error Rate (BER) simulator, Samsung BER simulator (SBERS), in order to evaluate the link compliance and all kinds of effects of link compliance in a real environment. SBERS allows to generate transmit pulse accurately by using the various parameters, and obtain the eye diagram and bathtub curve, which represents the performance of link, by calculating the transmit pulse and the measured frequency response characteristics. SBERS give results as same as real environment after taking account of distribution and value of noise. To verify the accuracy of simulator, we derive the simulated and measured result and compare eye opening. The difference came out to be within 5% error. It is possible to estimate the real environment and design the transmitter and receiver circuit effectively using new BER simulator, SBERS.

A control protocol architecture based on LonTalk protocol for power line data communications

This paper presents a LonTalk protocol architecture that can alleviate the burden of data communications in the Neuron chip. The proposed protocol is implemented with partly hardware and partly software. The physical layer and the MAC layer of the LonTalk protocol are implemented in hardware. The upper link layer of the LonTalk protocol is implemented with software. We verified the commercial feasibility of the proposed system through the power line tests with the existing LonWorks network. As a result, it is concluded that the proposed architecture provides increasing flexibility and decreasing cost of the system.

A 4 Gb/s/pin dual-reference simultaneous bidirectional I/O circuit for memory-bus interface

This paper proposes a receiver with dual reference levels and a pre-emphasis circuit, which reduces ISI and improves input margin and linearity characteristics by 100% for data communication in memory applications. A test chip fabricated with a 0.10 /spl mu/m 1.8 V CMOS memory process achieves a data rate of 4 Gb/s/pin.