Soo In Cho

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

For operating frequencies exceeding 500 MHz, the timing margin of the I/O interface is critical and requires the data input-output timing accuracy to be within 200 ps. To meet the requirement, the designed SDRAM adopts a digitally self-calibrated on-die-termination with linearity error of /spl plusmn/1% and achieves over 1.2 Gbps/pin stable operation by using window matching and latency control. The chip is fabricated in a 0.13 /spl mu/m triple-well DRAM process.

A 2.5 V 333 Mb/s/pin 1 Gb double data rate SDRAM

While on-chip data flight times approach a few tens of nanoseconds for gigabit-scale DRAMs, a bandwidth over 250 MHz requires data input and output timing accuracy within 0.3 ns. Although a high-speed data interface can be achieved using precise clock generators such as delay locked loop (DLL), skews due to a long data access path may cause loss of internal timing margins. Diminished timing margin may be detrimental to wave pipelining for high-bandwidth. This 1 Gb double data rate (DDR) SDRAM featuring ODIC chip with nonODIC package (OCNOP), cycle-time-adaptive wave pipelining (CTAWP), and variable stage analog DLL achieves high performance despite stringent processing variations in 0.14 /spl mu/m design rules.

A 800Mb/s/pin 2GB DDR2 SDRAM using an 80nm triple metal technology

A 1.8V, 800Mbit/s/pin, 2GB DDR2 SDRAM is developed using an 80nm triple metal technology. With the triple metal technology, NMOS precharge I/O scheme and statistical analysis, DDR800 4-4-4 performance is achieved at 1.8V. For mass production, a high-speed clock using an on chip PLL and an address-pin-reduction mode are employed.

A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing Scheme and Bang-Bang Jitter Reduced DLL Scheme

A 1.6Gb/s/pin 1Gb DDR3 SDRAM with a CAS latency of 8 at 1.5 V is developed using an 80 nm dual poly CMOS process, which consumes 30 mA of IDD2N and 160 mA of IDD4R. With an address queuing scheme and a self-timed IOSA, IDD4R current can be reduced by 18 mA. To achieve 1.6Gb/s/pin operation, a bang-bang jitter free DLL with a split phase interpolator is employed.

A 2.5 V, 20 Gbyte/s 288 M packet-based DRAM with enhanced cell efficiency and noise immunity

Multimedia and multi-tasking computing systems demand high bandwidth and multi-bank DRAMs. To meet these requirements, several challenges regarding the chip size penalty and noise concerns associated with multi-I/O lines should be resolved. This paper describes a 2.5-V, 288-Mb DRAM with a 32-bank architecture achieving a peak bandwidth of 2.0 GB/s using both 500-MHz differential clocks and 18-I/O organization. This chip features (1) an area- and performance-efficient chip architecture with well-mixed high-speed interface circuits with DRAM peripheral circuits to increase the cell efficiency, (2) a multi-level controlled equalizing scheme and a distributed sense amplifier-driving scheme to enhance the DRAM core timing margin while digressing from the conventional sub-wordline driving scheme, having 352 cells per sub-wordline, (3) an area-efficient column redundancy scheme with multiple fuse-boxes instead of excessive spare memory cell arrays for the multi-I/O architecture, (4) a zero-DC current receiver with a counter kick-back coupling scheme to reduce the reference coupling noise, and (5) a PVT (power, voltage, time) insensitive current control scheme.