Wook Kim

Statistical Leakage Estimation Based on Sequential Addition of Cell Leakage Currents

This paper presents a novel method for full-chip statistical leakage estimation that considers the impact of process variation. The proposed method considers the correlations among leakage currents in a chip and the state dependence of the leakage current of a cell for an accurate analysis. For an efficient addition of the cell leakage currents, we propose the virtual-cell approximation (VCA), which sums cell leakage currents sequentially by approximating their sum as the leakage current of a single virtual cell while preserving the correlations among leakage currents. By the use of the VCA, the proposed method efficiently calculates a full-chip leakage current. Experimental results using ISCAS benchmarks at various process variation levels showed that the proposed method provides an accurate result by demonstrating average leakage mean and standard deviation errors of 3.12% and 2.22%, respectively, when compared with the results of a Monte Carlo (MC) simulation-based leakage estimation. In efficiency, the proposed method also demonstrated to be 5000 times faster than MC simulation-based leakage estimations and 9000 times faster than the Wilkinsons method-based leakage estimation.

Improving the process variation tolerability of flip-flops for UDSM circuit design

The process variation of the ultra-deep submicron technology causes significant variation in the timing characteristics of flip-flops, and it can drop functional yield seriously, affecting system timing. This paper has two objectives. First, this paper investigates the sensitivities to process variation of four representative flip-flop architectures that are popularly used in digital circuit designs in respect of their functional robustness. Secondly, this paper proposes simple but effective methods to improve the process variation tolerability of those flip-flops. Experimental results on four benchmark flip-flops, which were optimized for minimum power-delay product, show that their variability of data-to-q delay reaches to 33.02% ∼ 46.13% and functional yield reaches to 79.93% ∼ 99.86%. Also, the experimental results clearly show that the proposed approaches improve the variability of data-to-q delay by 11.53% ∼ 44.78% and functional yield by 0.11% ∼ 24.41%.

Timing Criticality for Timing Yield Optimization

Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.

Incremental statistical static timing analysis with gate timing yield emphasis

Incremental analysis is indispensible for efficient circuit optimization, as it analyzes the effect by the modified circuit part only instead of analyzing a whole circuit again from beginning. This paper presents a new incremental statistical static timing analysis (SSTA) method, called timing yield-based incremental analysis (TYIA). TYIA uses the probability that the gate timing slack is non-negative to prune the timing change propagation after a gate replacement. In the experimental results using ISCAS-85 benchmarks, TYIA showed 2~5 times better accuracy in timing yield analysis at comparable efficiency, when compared to the existing incremental SSTA methods.

Facile approach to synthesize highly fluorescent multicolor emissive carbon dots via surface functionalization for cellular imaging

Luminescent nanomaterials are encouraging scaffolds for diverse applications such as chemical sensors and biosensors, imaging, drug delivery, diagnostics, catalysis, energy, photonics, medicine, and so on. Carbon dots (CDs) are a new class of luminescent carbonaceous nanomaterial that have appeared recently and reaped tremendous scientific interest. Herein, we have exploited a simple approach to prepare tuneable and highly fluorescent CDs via surface functionalization. The successful synthesis of CDs is manifested from several investigations like high-resolution transmission electron microscopy (HRTEM), X-ray diffraction (XRD), Fourier transform infrared spectroscopy (FTIR) and X-ray photoelectron spectroscopy (XPS). The CDs exhibit excellent water solubility and with increasing nitrogen content fluorescence quantum yield increases whereas cell toxicity decreases. The CD synthesized at high temperature (180u202f°C) shows very high quantum yield (more than 56%). The tuneable optical properties of CDs are systematically studied using UV-vis and fluorescence spectroscopy. The cell viability evaluation and in vitro imaging study reveals that the synthesized CDs can be employed as a potential fluorescent probe for bio-imaging without further modification.

Effect of local random variation on gate-level delay and leakage statistical analysis

In this paper, we analyzes the error due to the effects of local random variation on delay and leakage in the gate level statistical modeling. In experiments with various gates, without considering the local random variation showed over 20% of maximum error on the gate delay standard deviation, when compared with the results considering the local random variation. Moreover, in the aspect of leakage, without considering the local random variation causes maximum 10% of mean leakage error and over 300% of standard deviation error, when compared with the results considering the local random variation. Since conventional gate-level statistical model does not consider the local random variation, large local random variation may cause the significant error. Therefore, novel gate-level statistical modeling method considering the local random variation is required.

Assessment of using the statistical timing analysis software for the VLSI design at the macro level

Satisfying timing constraint is the most important issue in todays VLSI design. The recent increase of process variation, however, made it too difficult to predict the circuit timing accurately using traditional deterministic methods. Many statistical static timing analysis (SSTA) approaches have been proposed to deal with the impact of large process variation effectively. However, most of them focused on the gate-level design, and those for macro-level designs have not been well developed yet. This paper investigates the validity of applying SSTA to the macro-level designs by presenting preliminary experimental results that compare SSTA and the worst-case corner timing analysis in accuracy. In addition, this paper investigates how the process variation affects the usefulness of the macro-level SSTA.

Investigation of efficiency and accuracy on incremental SSTA

This paper compares the characteristics and performances of incremental statistical static timing analysis (SSTA) methods. In contrast to incremental analysis in the deterministic static timing analysis (STA), timing error is indispensable for an efficient incremental SSTA, and the efficiency and accuracy have a trade-off relation. We compared and analyzed the differences between the incremental STA and SSTA, and presented the error source of the incremental SSTA. From the experimental results by three major incremental analysis methods, we presented the relationship between the efficiency and accuracy in incremental SSTA. We showed as well that all tested incremental SSTA methods give relatively accurate results that errors are lower than 1% with the some sacrifice of the efficiency. However, the merits and demerits of each method differs to that of each others, we compared the merits and demerits of each method.

Comparison of characterization methods for statistical analysis of SoC designs

This paper compares characteristics and performances of characterization methods for statistical timing analysis and statistical leakage estimation. Two popular characterization methods, regular grid sampling and distribution based sampling are selected and their features, advantages and disadvantages are discussed. The experimental results performed with ISCAS benchmark circuits showed the accuracy of using two methods in statistical analysis. In statistical timing analysis, distribution based sampling, which is good approach when the variation is not large, shows good performance in terms of accuracy. However, in statistical leakage estimation, regular grid sampling, which is superior when the variation is very large, shows good performance.