Kyung Tae Do

Early-life-failure detection using SAT-based ATPG

Early-life failures (ELF) result from weak chips that may pass manufacturing tests but fail early in the field, much earlier than expected product lifetime. Recent experimental studies over a range of technologies have demonstrated that ELF defects result in changes in delays over time inside internal nodes of a logic circuit before functional failure occurs. Such changes in delays are distinct from delay degradation caused by circuit aging mechanisms such as Bias Temperature Instability. Traditional transition fault or robust path delay fault test patterns are inadequate for detecting such ELF-induced changes in delays because they do not model the demanding detection conditions precisely. In this paper, we present an automatic test pattern generation (ATPG) technique based on Boolean Satisfiability (SAT) for detecting ELF-induced delay changes at all gates in a given circuit. Our simulation results, using various circuit blocks from the industrial OpenSPARC T2 design as well as standard benchmarks, demonstrate the effectiveness and practicality of our approach in achieving high coverage of ELF-induced delay change detection. We also demonstrate the robustness of our approach to manufacturing process variations.

Thermal-aware body bias modulation for high performance mobile core

Thermal management, which dynamically throttles frequency and voltage, is de facto standard in high performance mobile SoC to sustain device surface temperature under specific level; and throttling must accompany with computation slowdown. To minimize performance loss, we present a new thermal management by using adaptive body bias which efficiently modulates speed and leakage current. The key problem is to optimize body voltage respect to performance as well as power in chip-to-chip process variation. We also propose a semicustom design flow with standard cells and commercial EDA tools for seamless adoption to commercial products. With the proposed method, we can reduce 12.3% of the quality loss caused by thermal management in a mobile SoC test vehicle. This is the first study and commercial use in thermal management at the best of our knowledge.

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics

Using 28nm test chips, we derive signatures for early-life failures (ELF) in both high-K/metal-gate transistors and ultra low-K inter-metal dielectrics. We also demonstrate that the derived ELF signatures can be successfully detected using a clock control technique. Our results can be utilized to overcome scaled-CMOS reliability challenges in several ways: 1. Low-cost ELF detection during on-line operation of robust systems without requiring expensive redundancy-based error detection techniques; 2. Effective ELF screening during production test while reducing stress time and/or stress levels associated with stress tests such as burn-in.

Adaptive delay monitoring for wide voltage-range operation

As process technology scales down, circuit delay variations become more and more serious due to manufacturing and environmental variations. The delay variations are hardly predictable and thus require additional design margin and impede the chance to reduce area and power consumption of a chip. One way to alleviate the problem is to measure the circuit delay at run-time and control the supply voltage accordingly through a closed-loop dynamic voltage and frequency scaling (closed-loop DVFS) scheme. The circuit delay is typically measured by a monitoring circuit. However, the key issue of this scheme is the delay mismatch between the monitoring circuit and the target circuit block such as a CPU or a GPU. A large delay mismatch might lose the advantage of closed-loop DVFS. And it becomes worse as the circuit block operates in a wider voltage-range. This paper proposes a novel adaptive delay monitoring scheme for a wide voltage-range operation, which provides a better delay correlation between the monitor and the target compared to conventional monitoring approaches. The proposed approach reduces the average error in the measured delay by up to 45% and the maximum error by up to 68%. The reduction of the error brings the decrease of design margin, resulting in a lower-power and lower-cost design.

Clock domain crossing aware sequential clock gating

Power has become the overriding concern for most modern electronic applications today. To reduce clock power, which is a significant portion of the dynamic power consumed by a design, sequential clock gating is increasingly getting used over and above combinational clock gating. With the shrinking device sizes and increasingly complex designs, data is frequently transferred from one clock domain to the other. The sequential clock gating optimizations can use signals from across sequential boundaries and thus, can introduce new clock domain crossing (CDC) violations which can cause catastrophic functional issues in the fabricated chip. Hence, it has become very important that sequential clock gating optimizations be CDC aware. In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings - this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art two-pass solution is leading to an almost complete loss of power savings.

Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation

As the semiconductor process technology continuously scales down, circuit delay variations due to manufacturing and environmental variations become more and more serious. These delay variations are hardly predictable and thus require an additional design margin, which impedes the chance to reduce the area and power consumption of a chip. One of the best solutions to alleviate this problem is to measure circuit delays at run time and control the supply voltage accordingly through a closed-loop dynamic voltage and frequency scaling (DVFS) scheme. The key issue of this scheme is the delay mismatch between the monitoring circuit and the target block. A large delay mismatch might lose the advantage of the closed-loop DVFS. It becomes much worse as a circuit block operates in wider voltage range, from near-threshold voltage to super-overdrive voltage. This paper proposes novel delay monitoring systems with multiple generic monitors for wide voltage range operation, which provide a better delay correlation between the monitoring circuit and the target block compared to conventional monitoring approaches. The proposed approaches reduce the maximum error by up to 91% for a popular processor core in a 14-nm FinFET process technology, thereby bring a decrease of design margin, lower-power, and/or lower-cost design.

Sequential analysis driven reset optimization to improve power, area and routability

Resets are required in the design to initialize the hardware for system operation and to force it into a known state for simulation or to recover from an error. Given the increasing design complexity and time-to-market pressures, figuring out the registers which do not require resets is extremely challenging. In this paper, we present a novel algorithm which uses observability based sequential analysis to identify the registers in design which do not require resets. With the proposed algorithm, we have seen that in some cases 70% registers in the design can have redundant resets. Further, with removal of the redundant resets on registers up to 22% sequential power savings and up to 3% area reduction post-layout can be obtained.

Comparison of characterization methods for statistical analysis of SoC designs

This paper compares characteristics and performances of characterization methods for statistical timing analysis and statistical leakage estimation. Two popular characterization methods, regular grid sampling and distribution based sampling are selected and their features, advantages and disadvantages are discussed. The experimental results performed with ISCAS benchmark circuits showed the accuracy of using two methods in statistical analysis. In statistical timing analysis, distribution based sampling, which is good approach when the variation is not large, shows good performance in terms of accuracy. However, in statistical leakage estimation, regular grid sampling, which is superior when the variation is very large, shows good performance.