Wutthinan Jeamsaksiri

Low-power 5 GHz LNA and VCO in 90 nm RF CMOS

The potential of 90 nm CMOS technology for low-power RF front-ends is demonstrated with fully integrated low-voltage Low-Noise Amplifiers (LNA) and Voltage-Controlled Oscillators (VCO). The 5.5 GHz LNA draws 3.5 mA from a 0.6 V supply with a measured power gain of 11.2 dB, and a 3.2 dB noise figure. The 6.3 GHz VCO has a phase noise of -118 dBc/Hz at 1 MHz offset, drawing 4.9 mA from a 1.2 V supply.

Integration of a 90nm RF CMOS technology (200GHz f/sub max/ - 150GHz f/sub T/ NMOS) demonstrated on a 5GHz LNA

The potential for low power RF systems on chip of a 90nm CMOS technology is demonstrated for the first time on a monolithic 5GHz low noise amplifier. This technology combines a portfolio of high Q passive components with high RF performances 70nm physical gate length NMOSFETs (200GHz f/sub max/ -150GHz f/sub T/) presenting a ratio power gain/current gain higher than 1 up to the maximum measurement frequency.

A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS

A 5.5 GHz fully integrated low-power ESD-protected low-noise amplifier (LNA), designed and verified in a 90 nm RF CMOS technology, is presented for the first time. This 9.7 mW LNA features a 13.3 dB power gain with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB.

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.

Surface modification of silicon dioxide, silicon nitride and titanium oxynitride for lactate dehydrogenase immobilization

Three different types of surface, silicon dioxide (SiO2), silicon nitride (Si3N4), and titanium oxynitride (TiON) were modified for lactate dehydrogenase (LDH) immobilization using (3-aminopropyl)triethoxysilane (APTES) to obtain an amino layer on each surface. The APTES modified surfaces can directly react with LDH via physical attachment. LDH can be chemically immobilized on those surfaces after incorporation with glutaraldehyde (GA) to obtain aldehyde layers of APTES-GA modified surfaces. The wetting properties, chemical bonding composition, and morphology of the modified surface were determined by contact angle (CA) measurement, Fourier transform infrared (FTIR) spectroscopy, and scanning electron microscopy (SEM), respectively. In this experiment, the immobilized protein content and LDH activity on each modified surface was used as an indicator of surface modification achievement. The results revealed that both the APTES and APTES-GA treatments successfully link the LDH molecule to those surfaces while retaining its activity. All types of tested surfaces modified with APTES-GA gave better LDH immobilizing efficiency than APTES, especially the SiO2 surface. In addition, the SiO2 surface offered the highest LDH immobilization among tested surfaces, with both APTES and APTES-GA modification. However, TiON and Si3N4 surfaces could be used as alternative candidate materials in the preparation of ion-sensitive field-effect transistor (ISFET) based biosensors, including lactate sensors using immobilized LDH on the ISFET surface.

A low-cost 90nm RF-CMOS platform for record RF circuit performance

A 90nm CMOS technology has been used as the baseline for a low-cost RF-CMOS platform, with improved analog/RF performances of the active and passive devices. The 65 nm gate length NMOS exhibits 240GHz peak f/sub max/ and 170GHz peak f /sub T/. A peak Q of 40@5GHz is measured for a symmetrical 2.7 nH above-IC inductor. This combination leads to a world record performance of a monolithic 5 GHz RF CMOS low noise amplifier presenting a very high gain of 18dB and very low noise figure of 1.5dB, for only 4.8mW power consumption.

Impact of scaling on analog/RF CMOS performance

Analog/RF CMOS design in deep-sub micron digital CMOS is particularly challenging due to conflicting device performance requirements. The continuous scaling of digital CMOS has resulted in cut-off frequencies (f/sub T/) above 100Hz. however this improvement comes at a cost of degraded output resistance and reduced intrinsic gain. The difficulty of integrating analog/RF and high-performance digital functions on a single chip are expected to increase with scaling. In particular, it becomes a major issue to maintain analog performance parameters like 1/f noise and matching together with new high-k gate dielectrics. A lower nominal supply voltage is clearly beneficial for designers of digital circuits (lower power consumption, higher speed), but it presents difficult challenges for their analog designer peers. This review article discusses a number of significant items for analog designs in present and future CMOS processes and possible ways to maintain/improve their analog/RF performances. We illustrate the current achievements on a 90 nm CMOS technology and give an overview of the different options opened for future technologies.

RFCMOS ESD protection and reliability

This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the fabrication of the LNA. The measurement procedures used for the evaluation of stand-alone devices and LNAs are described. The ESD performance of standard ESD protection devices is reviewed and presents results and discussions on the ESD reliability of various ESD protection methods employed from the device point of view, followed by an outlook on the future RF ESD challenges, and conclusions.

UV-enhanced photodetector with nanocrystalline-TiO 2 thin film via CMOS compatible process

This research presents nanocrystal titaniumdioxide (nanocrystal-TiO2) film deposition technique with CMOS compatible process [1] to extend the optical response bandwidth of silicon based photodetecting devices toward ultraviolet range [2]. The thin films were initially deposited as Titanium Nitride (TiN) using DC magnetron reactive sputtering system. It was then annealed under nitrogen atmosphere at 800°C. After analyzing crystal structures and surface morphology with X-ray diffraction and FE-SEM systems, it was found that the deposited thin films showed the crystal phase of TiO2 oriented along (200) plane of Rutile crystal structure with 50 nm grain size and increasing with film thickness. Using electroreflectance (ER) spectroscopy measurement [3], the bandgap of nanocrystal-TiO2 was revealed to be 3.16 eV. PN-heterojunction photodiodes were fabricated with Nanocrystal-TiO2/SiO2/p-Si structures. Interdigitated aluminum structures were used as electrodes. By varying the thickness of nanocrystal-TiO2 film, i.e. 30, 60, and 90 nm, the devices could response further into the UV range. The absorption edge wavelength investigated by photoresponse measurement was at 275 nm and shifting to the shorter wavelength as a function of the nanocrystal-TiO2 grain size due to quantum confinement phenomenon [4]. The nanocrystal-TiO2/SiO2/p-Si photodetector had dark current = 5.31nA (2V), photocurrent = 0.9 uA, rise time = 58 us, fall time = 47 us at 30 nm thickness of TiO2.

RFCV Test Structure Design for a Selected Frequency Range

The problems with the CV characterization on very leaky (thin) nitrided oxide are mainly due to the measurement precision and MOS gate dielectric model accuracy. By doing S-parameter measurement at RF frequency and using simple but reasonably accurate model. we can obtain proper CV curves for very thin nitrided gate dielectrics. Regarding the measurement frequency we propose a systematic method to find a frequency range in which we can select measurement frequencies for all biases to obtain a full CV curve. Moreover, we formulated the first order relationship between the measurement frequency range and the test structure design for CV characterization. With the established formulae, we redesigned the test structures and verified that the formulae can be used as a guideline for the test structure design for RFCV measurements.