X. Jehl

Single-donor ionization energies in a nanoscale CMOS channel

One consequence of the continued downward scaling of transistors is the reliance on only a few discrete atoms to dope the channel, and random fluctuations in the number of these dopants are already a major issue in the microelectronics industry. Although single dopant signatures have been observed at low temperatures, the impact on transistor performance of a single dopant atom at room temperature is not well understood. Here, we show that a single arsenic dopant atom dramatically affects the off-state room-temperature behaviour of a short-channel field-effect transistor fabricated with standard microelectronics processes. The ionization energy of the dopant is measured to be much larger than it is in bulk, due to its proximity to the buried oxide, and this explains the large current below threshold and large variability in ultra-scaled transistors. The results also suggest a path to incorporating quantum functionalities into silicon CMOS devices through manipulation of single donor orbitals.

Simple and controlled single electron transistor based on doping modulation in silicon nanowires

A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and therefore controlled by lithography. The source and drain capacitances have also been characterized. This design could be used to build more complex SET devices.

Individual charge traps in silicon nanowires

Abstract.We study anomalies in the Coulomb blockade spectrum of a quantum dot formed in a silicon nanowire. These anomalies are attributed to electrostatic interaction with charge traps in the device. A simple model reproduces these anomalies accurately and we show how the capacitance matrices of the traps can be obtained from the shape of the anomalies. From these capacitance matrices we deduce that the traps are located near or inside the wire. Based on the occurrence of the anomalies in wires with different doping levels we infer that most of the traps are arsenic dopant states. In some cases the anomalies are accompanied by a random telegraph signal which allows time resolved monitoring of the occupation of the trap. The spin of the trap states is determined via the Zeeman shift.

A CMOS silicon spin qubit

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

A two-atom electron pump

With the development of single-atom transistors, consisting of single dopants, nanofabrication has reached an extreme level of miniaturization. Promising functionalities for future nanoelectronic devices are based on the possibility of coupling several of these dopants to each other. This already allowed to perform spectroscopy of the donor state by d.c. electrical transport. The next step, namely manipulating a single electron over two dopants, remains a challenge. Here we demonstrate electron pumping through two phosphorus donors in series implanted in a silicon nanowire. While quantized pumping is achieved in the low-frequency adiabatic regime, we observe remarkable features at higher frequency when the charge transfer is limited either by the tunnelling rates to the electrodes or between the two donors. The transitions between quantum states are modelled involving a Landau–Zener transition, allowing to reproduce in detail the characteristic signatures observed in the non-adiabatic regime.

Few electron limit of n-type metal oxide semiconductor single electron transistors

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.

Detection of a large valley-orbit splitting in silicon with two-donor spectroscopy.

We measure a large valley-orbit splitting for shallow isolated phosphorus donors in a silicon gated nanowire. This splitting is close to the bulk value and well above previous reports in silicon nanostructures. It was determined using a double dopant transport spectroscopy which eliminates artifacts induced by the environment. Quantitative simulations taking into account the position of the donors with respect to the Si/SiO2 interface and electric field in the wire show that the values found are consistent with the device geometry.

A tunable, dual mode field-effect or single electron transistor

A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron island is accumulated under the front gate of the device (SET regime), or a field-effect transistor is obtained by pinching off a bottom channel with a negative front gate voltage. The gradual transition between these two cases is observed. This dual function uses both vertical and horizontal tunable potential gradients in non-overlapped silicon-on-insulator channel.

Few-electron edge-state quantum dots in a silicon nanowire field-effect transistor.

We investigate the gate-induced onset of few-electron regime through the undoped channel of a silicon nanowire field-effect transistor. By combining low-temperature transport measurements and self-consistent calculations, we reveal the formation of one-dimensional conduction modes localized at the two upper edges of the channel. Charge traps in the gate dielectric cause electron localization along these edge modes, creating elongated quantum dots with characteristic lengths of ∼10 nm. We observe single-electron tunneling across two such dots in parallel, specifically one in each channel edge. We identify the filling of these quantum dots with the first few electrons, measuring addition energies of a few tens of millielectron volts and level spacings of the order of 1 meV, which we ascribe to the valley orbit splitting. The total removal of valley degeneracy leaves only a 2-fold spin degeneracy, making edge quantum dots potentially promising candidates for silicon spin qubits.

Compact silicon double and triple dots realized with only two gates

We report electronic transport on silicon double and triple dots created with the optimized number of two gates. Using silicon nitride spacers two dots in series are created below two top gates overlapping a silicon nanowire. Coupling between dots is controlled by gate voltages. A third dot is created either by combined action of gate voltages or local doping depending on the spacers length. The main characteristics of the triple dot stability diagram are quantitatively fitted.