Dharmraj Kotekar-Patil

A CMOS silicon spin qubit

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Few electron limit of n-type metal oxide semiconductor single electron transistors

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.

Electrically driven electron spin resonance mediated by spin–valley–orbit coupling in a silicon quantum dot

The ability to manipulate electron spins with voltage-dependent electric fields is key to the operation of quantum spintronics devices, such as spin-based semiconductor qubits. A natural approach to electrical spin control exploits the spin–orbit coupling (SOC) inherently present in all materials. So far, this approach could not be applied to electrons in silicon, due to their extremely weak SOC. Here we report an experimental realization of electrically driven electron–spin resonance in a silicon-on-insulator (SOI) nanowire quantum dot device. The underlying driving mechanism results from an interplay between SOC and the multi-valley structure of the silicon conduction band, which is enhanced in the investigated nanowire geometry. We present a simple model capturing the essential physics and use tight-binding simulations for a more quantitative analysis. We discuss the relevance of our findings to the development of compact and scalable electron–spin qubits in silicon.Silicon-based qubits: electrically-driven manipulation of spins in double quantum dotsWeak spin–orbit effects in silicon can be exploited to electrically drive electron-spin resonance in a silicon nanowire quantum dot device with low-symmetry confinement potential. Andrea Corna and colleagues at Grenoble’s CEA and University Grenoble Alpes achieved this by fabricating a silicon nanowire device over a silicon-on-insulator wafer, on which the gate accumulation voltages can define two corner quantum dots. Quantum confinement allows the coupling of spin and valley degrees of freedom via spin–orbit coupling, despite its inherent weakness in silicon, when the energy splitting between the valley energy eigenstates matches the magnetic field-induced Zeeman spin splitting. The observation of electric-dipole spin-valley resonance demonstrates the potential of spin–orbit coupling for realizing electric-field-mediated spin control, which will be crucial for large-scale integration of silicon-based spin qubits.

Pauli blockade in a few-hole PMOS double quantum dot limited by spin-orbit interaction

We report on the hole compact double quantum dots fabricated using a conventional CMOS technology. We provide the evidence of Pauli spin blockade in the few hole regime that is relevant to spin qubit implementations. A current dip is observed around zero magnetic field, in agreement with the expected behavior for the case of strong spin-orbit. We deduce an intradot spin relaxation rate ≈120 kHz for the first holes, an important step towards a robust hole spin-orbit qubit.

Mass Production of Silicon MOS-SETs: Can We Live with Nano-Devices’ Variability?

Abstract It is very important to study variability of nanodevices because the inability to produce large amounts of identical nanostructures is eventually a bottleneck for any application. In fact variability is already a major concern for CMOS circuits. In this work we report on the variability of dozens of silicon single-electron transistors (SETs). At room temperature their variability is compared with the variability of the most advanced CMOS FET i.e. the ultra thin Silicon-on-Insulator Multiple gate FET (UT SOI MuGFET). We found that dopants diffused from Source –Drain into the edge of the undoped channel are the main source of variability. This emphasizes the role of extrinsic factors like the contact junctions for variability of any nanodevice.

Level Spectrum and Charge Relaxation in a Silicon Double Quantum Dot Probed by Dual-Gate Reflectometry

We report on dual-gate reflectometry in a metal-oxide-semiconductor double-gate silicon transistor operating at low temperature as a double quantum dot device. The reflectometry setup consists of two radio frequency resonators respectively connected to the two gate electrodes. By simultaneously measuring their dispersive responses, we obtain the complete charge stability diagram of the device. Electron transitions between the two quantum dots and between each quantum dot and either the source or the drain contact are detected through phase shifts in the reflected radio frequency signals. At finite bias, reflectometry allows probing charge transitions to excited quantum-dot states, thereby enabling direct access to the energy level spectra of the quantum dots. Interestingly, we find that in the presence of electron transport across the two dots the reflectometry signatures of interdot transitions display a dip-peak structure containing quantitative information on the charge relaxation rates in the double quantum dot.

Si CMOS platform for quantum information processing

We report the first quantum bit (qubit) device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot (QD) defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself. By demonstrating qubit functionality in a conventional transistor-like layout and process flow, this result bears relevance for the future up-scaling of qubit architectures, including the opportunity of their co-integration with “classical” Si CMOS control circuitry.

SOI technology for quantum information processing

We present recent progress towards the implementation of a scalable quantum processor based on fully-depleted silicon-on-insulator (FDSOI) technology. In particular, we discuss an approach where the elementary bits of quantum information — so-called qubits — are encoded in the spin degree of freedom of gate-confined holes in p-type devices. We show how a hole-spin can be efficiently manipulated by means of a microwave excitation applied to the corresponding confining gate. The hole spin state can be read out and reinitialized through a Pauli blockade mechanism. The studied devices are derived from silicon nanowire field-effect transistors. We discuss their prospects for scalability and, more broadly, the potential advantages of FDSOI technology.

Pauli spin blockade in CMOS double quantum dot devices: Pauli spin blockade in CMOS double quantum dot devices

Silicon quantum dots are attractive candidates for the development of scalable, spin-based qubits. Pauli spin blockade in double quantum dots provides an efficient, temperature independent mechanism for qubit readout. Here we report on transport experiments in double gate nanowire transistors issued from a CMOS process on 300 mm silicon-on-insulator wafers. At low temperature the devices behave as two few-electron quantum dots in series. We observe signatures of Pauli spin blockade with a singlet-triplet splitting ranging from 0.3 to 1.3 meV. Magneto-transport measurements show that transitions which conserve spin are shown to be magnetic-field independent up to B = 6 T.

Charge granularity in single electron transistors with polysilicon gates

Low temperature electron transport measurements of single electron transistors fabricated in advanced CMOS technology with polysilicon gates not only exhibit clear Coulomb blockade behavior but also show a large number of additional conductance fluctuations in the nonlinear regime. By comparison with simulations these features are quantitatively attributed to the effects of discretely charged islands in the polysilicon gates.