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Leakage optimization of ultra-shallow junctions formed by solid phase epitaxial regrowth

Ultra-shallow p+ junctions formed by solid phase epitaxial regrowth (SPER) have promise for sub-65 nm CMOS technologies. Due to above-equilibrium solid solubilities and minimal diffusion, such junctions can far outperform spike-annealed junctions in terms of resistance, abruptness, and depth. However, the low-temperature annealing does not dissolve the end of range defects creating concerns for junction leakage in the device. In this work, we show how SPER junctions can be optimized to meet the ITRS junction profile and low-power leakage requirements of the 45 nm CMOS node [International Technology Roadmap for Semiconductors (Semiconductor Industry Association, San Jose, CA, 2001)]. Diode leakage is shown to decrease with Ge amorphization depth and B dose and energy. Leakage is shown to increase dramatically with the background doping level. Increasing the regrowth, or post-annealing, thermal budget improves leakage and can be optimized to avoid deactivation. The inclusion of a preanneal does not affect t...

A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture. In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness ( 4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Enhanced boron activation in silicon by high ramp-up rate solid phase epitaxial regrowth

We investigate the influence of thermal conditions during solid phase epitaxial regrowth (SPER) on the electrical activation level of boron in preamorphized silicon, both with respect to heating ramp rates and the use of low temperature preanneals. Enhancement of electrically active boron concentration by 36% is observed for activation with the fastest ramp rate (487°C∕s) compared to the slowest one (1°C∕s). An important clustering pathway occurs within the amorphous silicon phase (during low temperature preanneal) prior to completion of the SPER process. In these junctions boron deactivation during isochronal post-annealing is almost independent on the maximum boron activation level.

Continuity in the development of ultra shallow junctions for 130-45 nm CMOS: the tool and annealing methods

The roadmap for ultra-shallow junction formation (USJ) includes implant spike anneal and solid-phase epitaxial re-growth. The roadmap for the junction contacts foresees transition from CoSi/sub 2/ to NiSi. The processes in the roadmap require extreme capabilities from RTP tools: heat-up and cool-down rates of hundreds of degrees per second, no pattern/emissivity dependence, precise temperature control, and operation at low temperature (starting from 200/spl deg/C for NiSi formation). This paper describes a tool which enables continuity in the development of USJ for current and future technology nodes. It provides high ramp rates (300-900/spl deg/C/sec), and operates in the temperature range of 100-1100/spl deg/C with precise temperature control.

NiSi contact formation - process integration advantages with partial Ni conversion

Investigations for next generation contacts of silicon and SiGe devices show that a 2-step nickel salicidation process is favorable over a single step NiSi and over CoSi2 in every respect and can be introduced easily in existing and advanced not fully depleted CMOS flows once the post silicidation thermal treatments can be kept below 700degC. Partial conversion for the deposited Ni layer to Ni2 Si in a first RTP1 step at temperatures as low as 250degC avoids the reverse linewidth effect and enables superior uniformities over complete conversion. A second RTP2 step at typically 450degC is used to form low resistivity NiSi with less silicon consumption and lower contact resistivities than todays CoSi2 contacts. Challenging integration issue are peripheral leakage currents, that are likely to be related to undesired low temperature pyramidal NiSi2 formation and spiking

SPER junction optimisation in 45 nm CMOS devices

Ultra-shallow junction formation by solid phase epitaxial regrowth (SPER) has been shown to produce excellent junction profiles beyond that of conventional spike annealing. However residual damage can degrade various aspects of the transistor performance, annihilating any:improvement due to the junction profile. In this work we look at optimizing the junction and channel conditions to meet the dopant profile and transistor requirements for the 45 nm CMOS node. We show how an optimised junction implant and low temperature SPER spike anneal can further increase the activation level and profile of the junction. In devices we show results on the effect of SPER processing on both the substrate and gate doping. This includes junction overlap, channel deactivation, contact resistance, junction leakage, poly depletion, and gate leakage. We address each of these concerns for both pMOS and nMOS and identify what are the main strengths and weaknesses of SPER in devices.

NiPt silicide agglomeration accompanied by stress relaxation in NiSi(010) ∥ Si(001) grains

Pt-doped Ni (NiPt) silicide agglomeration in terms of NiSi crystal orientation, Pt segregation at the NiSi/Si interface, and residual stress is studied for the first time. In the annealing of Ni monosilicide (NiSi), the growth of NiSi grains whose NiSi b-axes are aligned normal to Si(001) [NiSi(010) ∥ Si(001)] with increasing Pt segregation at the NiSi/Si interface owing to a high annealing temperature was observed. The residual stress in NiSi(010) ∥ Si(001) grains also increases with increasing annealing temperature. Furthermore, the recrystallization of NiSi(010) ∥ Si(001) grains with increasing residual stress continues through additional annealing after NiSi formation. After the annealing of NiSi(010) ∥ Si(001) grains with their strain at approximately 2%, the start of NiPt silicide agglomerates accompanied by stress relaxation was observed. This preferential recrystallization of NiSi(010) ∥ Si(001) grains with increasing residual stress is considered to enhance the NiPt silicide agglomeration.

Advanced PMOS Device Architecture for Highly-Doped Ultra-Shallow Junctions

In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (Ion=450 µA/µm at Ioff=250 nA/µm for devices with Lg\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.

Pattern-Dependent Heating of 3D Structures

Spike anneals based on radiation and conduction heating are carried out on silicon wafers with 12xl2mm2 patterned areas; these areas are covered with trenches with varying dimensions, thermally isolated from each other by large unpatterned silicon areas. The width of the trenches varies from 150-4500nm; the depths are 400 and 800nm. It is found that lamp-based heating with heatrup rates varying from 50-180degC/s results in temperature gradients of 10-45degC. In case of conduction heating in the conduction-based system (Levitor) no pattern-dependent temperature gradients are observed. A theoretical model was made such as to calculate the temperature gradient generated by the radiation heating process. In case of wide trenches, this model appears to predict the observed gradients reasonably well. However, in case of trenches < 450nm, the model overestimates the experimentally observed gradients.

Diffusion and activation of Boron and Phosphorus in preamorphized and crystalline Germanium using ultra fast spike anneal

In this work, the influence of a pre-amorphization implant (PAI) combined with a single-step spike anneal on the junction formation in Germanium is inverstigated, both for n-type dopant with Phosphorus (P) as well as for p-type dopant Boron (B). The experiments were performed on a 1.5µm Germanium (Ge) epi-layer onto 200mm Silicon (Si) substrate. After implantation both with or without PAI, the dopant activation was achieved using a single step, conductive, spike anneal (ranging 550ºC–900ºC) in a ASM Levitor® system. Junction depth (Xj) and electrical activation levels (Nact) were characterized using secondary-ion-mass spectroscopy (SIMS) and sheet resistance Rs measurements. The results show that the combination of the high ramp rates with single step spike anneal on the one hand and PAI on the other hand, improved junctions characteristics compared to standard implant and RTP (Rapid Thermal Processing) conditions. The SIMS results show a reduction of junction depth for pre-amorphized junction after activation annealing up to 20% with P and 42% with B at 5×1018 cm−3 dopant concentration. In addition, electrical activation levels up to 4,95×1020 cm−3 were achieved for the p-type implants.