X.S. Hu

Nanomagnet logic: progress toward system-level integration.

Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input–output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins. This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain--using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.

Experimental Demonstration of Fanout for Nanomagnetic Logic

Nanomagnet logic (NML) shows great promise as an alternative to conventional digital architectures. We present the first experimental demonstration of fanout using magnetizations of nanomagnets in the NML scheme. Specifically, we show magnetic force microscopy images of functioning fanout circuits.

Preference-driven hierarchical hardware/software partitioning

We present a hierarchical evolutionary approach to hardware/software partitioning for real-time embedded systems. In contrast to most previous approaches, we apply a hierarchical structure and dynamically determine the granularity of tasks and hardware modules to adaptively optimize the solution while keeping the search space as small as possible. Two new search operators are described, which exploit the proposed hierarchical structure. Efficient ranking is another problem addressed. Imprecisely specified multiple attribute utility theory has the advantage of constraining the solution space computation overhead. We propose a new technique to reduce the overhead. Experiment results show that our algorithm is both effective and efficient.

Non-majority magnetic logic gates: a review of experiments and future prospects for 'shape-based' logic.

We discuss the experimental demonstration of non-majority, two-input, nanomagnet logic (NML) AND and OR gates. While gate designs still can incorporate the symmetric, rounded-rectangle magnets used in the three-input majority gate experiments by Imre (2006 Sciencexa0311xa0205-8), our new designs also leverage magnets with an edge that has a well-defined slant. In rectangular and ellipsoid nanomagnets, the easy axis of the device coincides with its longer edge. For a magnet with a slanted edge, the easy and hard axes are tilted, and magnetic fields applied along the (geometrical) hard axis alone can set the easy axis magnetization state. This switching phenomenon can be employed to realize NML Boolean logic gates with both reduced footprints and critical path delays. Experimental demonstrations of two-input AND and OR gates are supported by corresponding micromagnetic simulations with temperature effects associated with a 300xa0K environment. Simulations suggest that the time evolution of experimentally demonstrated structures is correct, and that designs can also tolerate clock field misalignment. Additionally, simulations suggest that a slanted-edge compute magnet can (i) be driven by two anti-ferromagnetically ordered lines of NML devices (for input) and (ii) drive an anti-ferromagnetically ordered line (for output). Both are essential if slanted-edge devices are to be used in NML circuits. We conclude with a discussion of extensibility and scaling prospects for shape-based computation with nanomagnets.

Bridging the gap between nanomagnetic devices and circuits

This paper looks at designing circuit elements that will be constructed with nanoscale magnets within the Quantum-dot Cellular Automata (QCA) computational paradigm. In magnetic QCA (MQCA) logical operations and dataflow are accomplished by manipulating the polarizations of nanoscale magnets. Wires and gates have already been experimentally demonstrated at room temperature. However, to realize more complex circuits - and eventually systems - more than just wires and gates in isolation are required. For example, gates must be inter-connected, signals must cross, etc. All structures must be controlled by the envisioned drive circuitry. In this paper, structures that will facilitate these circuit-level tasks are presented for the first time.

Magnetic Properties of Enhanced Permeability Dielectrics for Nanomagnetic Logic Circuits

Enhanced permeability dielectric (EPD) samples were fabricated in an ultra-high-vacuum magnetron sputtering system, and their magnetic properties were studied by a variable-temperature vibrating sample magnetometer. EPDs were fabricated with layers of CoFe forming uniform particles separated by MgO dielectric as insulator. The optimal sample has peak relative low-field permeability (μ_r) of 452, saturation magnetization (M_s) of 636 emu/cm³ and magnetization at 100 Oe (M_{100 Oe}) of 398 emu/cm³. Effect of low temperature is discussed, and measurements show that the EPD remains superparamagnetic at 173 K; μ_r, M_s and M_{100 Oe} values at reduced temperatures are higher than those at room temperature. The sample is ferromagnetic at 100 K.

Experimental demonstration of fanout for Nanomagnet Logic

Nanoscale magnets can process and move information via fringing field interactions. Wires, gates, and inverters have been demonstrated (Fig. 1a-c)1 - all at room temperature. Nanomagnet Logic (NML) devices can be made with standard lithographic techniques, and even with drive circuitry overhead, energy/performance gains over CMOS are possible2. Still, demonstrating wires and gates in isolation does not equate to a deployable digital system. For systems, it is widely accepted that a technology must meet five criteria3 - (i) a device should have non- linear response characteristics, (ii) the output of one device must drive another, (iii) unwanted dataflow (or feedback) should not occur, (iv) a device must enable a functionally complete logic set, and (v) power amplification (or gain greater than 1) is needed. We report experimental demonstration of the fifth tenet of digital logic - fanout.

Boolean and non-boolean nearest neighbor architectures for out-of-plane nanomagnet logic

We present the design and simulation of information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic - or oNML). We first describe the design and evaluation of oNML hardware that can identify instances of a preprogrammed bit sequence in streaming data. Systolic arrays (that process information using Boolean logic gates) are employed as a system-level architecture which can (i) mitigate less desirable features of the oNML device architecture (nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor), and (ii) exploit unique features of the device architecture (non-volatility and inherently pipelined logic with no overhead). We conclude the paper with a discussion as to how oNML might be employed for non-Boolean information processing. A simple image processing function is used as an initial case study.

Design Tradeoffs for Improved Performance in MQCA-Based Systems

This paper looks at circuits and systems made from nanoscale magnets. We leverage physical level simulation to show how to extend initial experimental work - where wires and gates with nanometer feature sizes have been demonstrated at room temperature - to show how one might make design tradeoffs to improve both the performance and reliability of more complex systems.

Demonstration of Field-Coupled Input Scheme on Line of Nanomagnets

We report an electric and on-chip field-coupled input scheme for nanomagnet logic (NML). Deterministic control over the switching of a nanomagnet is demonstrated by applying synchronous clock and bias fields to first place the device in 0°/metastable state, and then tilt its magnetization in the appropriate direction. The clock field is generated on-chip by a CMOS-compatible clock line, while the bias field is generated by an input structure integrated with the clock line. Successful propagation of input data through ferromagnetic and antiferromagnetic coupling was observed along an L shaped NML line. This scheme can serve as an electric-magneto interface between CMOS and an NML circuit for NML inputs.