X. Sun

The MAPS based PXL vertex detector for the STAR experiment

The Heavy Flavor Tracker (HFT) was installed in the STAR experiment for the 2014 heavy ion run of RHIC. Designed to improve the vertex resolution and extend the measurement capabilities in the heavy flavor domain, the HFT is composed of three different silicon detectors based on CMOS monolithic active pixels (MAPS), pads and strips respectively, arranged in four concentric cylinders close to the STAR interaction point. The two innermost HFT layers are placed at a radius of 2.7 and 8 cm from the beam line, respectively, and accommodate 400 ultra-thin (50 μ m) high resolution MAPS sensors arranged in 10-sensor ladders to cover a total silicon area of 0.16 m2. Each sensor includes a pixel array of 928 rows and 960 columns with a 20.7 μ m pixel pitch, providing a sensitive area of ~ 3.8 cm2. The architecture is based on a column parallel readout with amplification and correlated double sampling inside each pixel. Each column is terminated with a high precision discriminator, is read out in a rolling shutter mode and the output is processed through an integrated zero suppression logic. The results are stored in two SRAM with ping-pong arrangement for a continuous readout. The sensor features 185.6 μ s readout time and 170 mW/cm2 power dissipation. The detector is air-cooled, allowing a global material budget as low as 0.39% on the inner layer. A novel mechanical approach to detector insertion enables effective installation and integration of the pixel layers within an 8 hour shift during the on-going STAR run.In addition to a detailed description of the detector characteristics, the experience of the first months of data taking will be presented in this paper, with a particular focus on sensor threshold calibration, latch-up protection procedures and general system operations aimed at stabilizing the running conditions. Issues faced during the 2014 run will be discussed together with the implemented solutions. A preliminary analysis of the detector performance meeting the design requirements will be reported.

MAPS development for the ALICE ITS upgrade

Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Several sensor chip prototypes have been developed and produced to optimise both charge collection and readout circuitry. The chips have been characterised using electrical measurements, radioactive sources and particle beams. The tests indicate that the sensors satisfy the ALICE requirements and first prototypes with the final size of 1.5 × 3 cm2 have been produced in the first half of 2014. This contribution summarises the characterisation measurements and presents first results from the full-scale chips.

LOCx2, a low-latency, low-overhead, 2 × 5.12-Gbps transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade

In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. LOCx2 is fabricated with a commercial 0.25-μm Silicon-on-Sapphire CMOS technology and is packaged in a 100-pin QFN package. The power consumption of LOCx2 is about 843 mW.

8-Gbps-per-channel radiation-tolerant VCSEL drivers for the LHC detector upgrade

We present ASIC designs of VCSEL drivers for a single VCSEL (LOCld1), two individual VCSELs (LOCld2) and a four-channel VCSEL array (LOCld4). This work is for new detector readout systems needed in the Large Hadron Collider upgrade program. All ASICs are fabricated in a commercial 0.25-μ m Silicon-on-Sapphire CMOS technology. LOCld1 and LOCld2 have passed the 8-Gbps and 10-Gbps eye mask tests. Operating at 8 Gbps data rate, the measured total jitter of LOCld1 and LOCld2 is less than 30 ps, and the power comsuption is about 200 mW per channel with 6-mA bias current and 6.4-mA modulation current. The radiation tolerance of LOCld1 has been qualified with x-ray and high-energy neutron beam test.

The STAR Heavy Flavor Tracker PXL detector readout electronics

The Heavy Flavor Tracker (HFT) is a recently installed micro-vertex detector upgrade to the STAR experiment at RHIC, consisting of three subsystems with various technologies of silicon sensors arranged in 4 concentric cylinders. The two innermost layers of the HFT close to the beam pipe, the Pixel (PXL) subsystem, employ CMOS Monolithic Active Pixel Sensor (MAPS) technology that integrate the sensor, front-end electronics, and zero-suppression circuitry in one silicon die. This paper presents selected characteristics of the PXL detector part of the HFT and the hardware, firmware and software associated with the readout system for this detector.

Experience from the construction and operation of the STAR PXL detector

A new silicon based vertex detector called the Heavy Flavor Tracker (HFT) was installed at the Soleniodal Tracker At RHIC (STAR) experiment for the Relativistic Heavy Ion Collider (RHIC) 2014 heavy ion run to improve the vertex resolution and extend the measurement capabilities of STAR in the heavy flavor domain. The HFT consists of four concentric cylinders around the STAR interaction point composed of three different silicon detector technologies based on strips, pads and for the first time in an accelerator experiment CMOS monolithic active pixels (MAPS) . The two innermost layers at a radius of 2.8 cm and 8 cm from the beam line are constructed with 400 high resolution MAPS sensors arranged in 10-sensor ladders mounted on 10 thin carbon fiber sectors giving a total silicon area of 0.16 m2. Each sensor consists of a pixel array of nearly 1 million pixels with a pitch of 20.7 μm with column-level discriminators, zero-suppression circuitry and output buffer memory integrated into one silicon die with a sensitive area of ~ 3.8 cm2. The pixel (PXL) detector has a low power dissipation of 170 mW/cm2, which allows air cooling. This results in a global material budget of 0.5% radiation length per layer for detector used in this run. A novel mechanical approach to detector insertion allows for the installation and integration of the pixel sub detector within a 12 hour period during an on-going STAR run. The detector specifications, experience from the construction and operation, lessons learned and initial measurements of the PXL performance in the 200 GeV Au-Au run will be presented.

Characterization of the column-based priority logic readout of Topmetal-II− CMOS pixel direct charge sensor

We present the detailed study of the digital readout of Topmetal-II- CMOS pixel direct charge sensor. Topmetal-II- is an integrated sensor with an array of 72X72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators with individually DAC settable thresholds in each pixel. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic is fully combinational hence there is no clock distributed in the pixel array. Sequential logic and clock are placed on the peripheral of the array. We studied the detailed working behavior and performance of this readout, and demonstrated its potential in imaging applications.

Topmetal-II−: a direct charge sensor for high energy physics and imaging applications

Topmetal-II−, a direct charge sensor, was manufactured in an XFAB 350 nm CMOS process. The Topmetal-II− sensor features a 72 × 72 pixel array with an 83 μm pixel pitch which collects and measures charge directly from the surrounding media. We introduce the implementation of the circuitry in the sensor including an analogue readout channel and a column based digital readout channel. The analogue readout channel allows the access to the full waveform from each pixel through a time-shared multiplexing. The digital readout channel records hits identified by an individually settable threshold in each pixel. Some simulation and preliminary test results are also discussed.