Xia Zheng

Application of complex-network theories to the design of short-length low-density-paritycheck codes

Study of complex networks has been conducted across many fields of science, including computer networks, biological networks and social networks. Characteristics of different types of complex networks such as random networks, regular-coupled networks, small-world networks and scale-free networks have been discovered by researchers. Application of such network properties to solve engineering problems, however, is still at the infancy stage. In this study, we make one of the first attempts in applying complex network theories to communications engineering. In particular, inspired by the shortest-average-path-length property of scale-free networks, we design short-length low-density-parity-check (LDPC) codes with an aim to shortening the average distance between any two variable nodes. We will also compare the error performance, both theoretically and by simulations, of the proposed codes with those of other well-known LDPC codes.

Evaluation of the Extremely Low Block Error Rate of Irregular LDPC Codes

In this paper, we attempt to evaluate irregular LDPC code performance at the high SNR region using the importance sampling (IS) approach in conjunction with primary-trapping-set identification. Results have indicated that our proposed IS scheme can produce speed-up gains up to 3.9 × 109 times compared with Monte Carlo simulations.

STUDY OF BIFURCATION BEHAVIOR OF LDPC DECODERS

The use of low-density-parity-check (LDPC) codes in coding digital messages has aroused much research interest because of their excellent bit-error performance. The behavior of the iterative LDPC decoders of finite length, however, has not been fully evaluated under different signal-to-noise conditions. By considering the finite-length LDPC decoders as high-dimensional nonlinear dynamical systems, we attempt to investigate their dynamical behavior and bifurcation phenomena for a range of signal-to-noise ratios (SNRs). Extensive simulations have been performed on both regular and irregular LDPC codes. Moreover, we derive the Jacobian of the system and calculate the corresponding eigenvalues. Results show that bifurcations, including fold, flip and Neimark–Sacker bifurcations, are exhibited by the LDPC decoder. Results are useful for optimizing the choice of parameters that may enhance the effectiveness of the decoding algorithm and improve the convergence rates.

Performance evaluation of irregular low-density parity-check codes at high signal-to-noise ratio

Elementary trapping sets (ETSs) have been found to be the main cause of error floor in the decoding of low-density parity-check (LDPC) codes. Moreover, irregular LDPC codes that avoid harmful [w; u; e] ETSs have been constructed and have shown to possess superior error performance compared with other LDPC codes. In this paper, we attempt to evaluate irregular LDPC code performance under an additive white Gaussian noise channel within the high SNR region using the importance sampling (IS) approach in conjunction with the identification of [w; u; e] ETSs. For any given irregular LDPC code, we will first apply a three-step method that aims to search as many ETSs within the code as possible. Then, we will classify these ETSs into different groups based on their labels, i.e., [w; u; e]s. Further, by dividing the error region into various sub-regions centered by ETSs, we apply the IS simulator to evaluate the error rate of each of the sub-regions. Based on the error rates of all the sub-regions, we can estimate the overall error rate of the LDPC code. Results have indicated that our proposed IS scheme can produce speed-up gains up to 3.9×109 times compared to Monte Carlo simulations.

Techniques for improving block error rate of LDPC decoders

In the study of low-density-parity-check (LDPC) codes, most researchers are interested in their bit error rate performance. However, block error rate (BLER) is another important measure of the system performance because it provides the rate at which the blocks/packets need to be re-sent again - the smaller the better. In this paper, we apply a simple feedback technique to the decoding of LDPC codes. Extensive simulations have been performed. Results show that the proposed method can effectively improve the BLER of the codes at the waterfall region while not degrading the BER performance at the high SNR region

Study of nonlinear dynamics of LDPC decoders

Low-density-parity-check (LDPC) codes have aroused much research interest because of their excellent bit error performance. The behaviour of the iterative LDPC decoders, however, has not been fully investigated at all signal-to-noise ratios (SNRs). By considering the LDPC decoders as high-dimensional nonlinear dynamical systems, we attempt to study the corresponding phase trajectories at different SNR values. By having an in-depth understanding of the decoder behaviour, engineers should be able to design more effective and efficient decoders.

Construction of short-length LDPC codes with low error floor

It has been known that stopping sets and trapping sets are the main contributors to error floors exhibited by short-length low-density parity-check (LDPC) codes. In this work, a new metric called ldquoapproximate cycle set extrinsic message degree (ACSE)rdquo is defined to help removing stopping sets with small size and bad trapping sets. Based on the new metric, we propose a code-construction algorithm that produces LDPC codes with very low error floors. Finally, we compare the error rates between codes produced by the proposed algorithm and MacKay code.

Constructing high-rate scale-free LDPC codes

Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the “pure” SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes.

Differentiating trapping sets with the same label [w; u]

Trapping sets (TSs) have been known to contribute to errors in the decoding of low-density parity-check (LDPC) codes, particularly at the high signal-to-noise ratio (SNR) region. Moreover, TSs with the same label [w; u] are considered equivalent under the automorphism of the graph of a regular code. But according to our our simulations, TSs with the same label [w; u] are producing different error rates in the case of irregular codes. In this paper, we will identify and explain the cause of the differences in error rates for TSs with the same label. Further, we will propose a simple mechanism to differentiate these TSs.