Xiang-Zheng Bo

On-chip natural assembly of silicon photonic bandgap crystals

Photonic bandgap crystals can reflect light for any direction of propagation in specific wavelength ranges. This property, which can be used to confine, manipulate and guide photons, should allow the creation of all-optical integrated circuits. To achieve this goal, conventional semiconductor nanofabrication techniques have been adapted to make photonic crystals. A potentially simpler and cheaper approach for creating three-dimensional periodic structures is the natural assembly of colloidal microspheres. However, this approach yields irregular, polycrystalline photonic crystals that are difficult to incorporate into a device. More importantly, it leads to many structural defects that can destroy the photonic bandgap. Here we show that by assembling a thin layer of colloidal spheres on a silicon substrate, we can obtain planar, single-crystalline silicon photonic crystals that have defect densities sufficiently low that the bandgap survives. As expected from theory, we observe unity reflectance in two crystalline directions of our photonic crystals around a wavelength of 1.3 micrometres. We also show that additional fabrication steps, intentional doping and patterning, can be performed, so demonstrating the potential for specific device applications.

Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates

We fabricated CMOS circuits from polycrystalline silicon films on steel foil substrates at process temperatures up to 950/spl deg/C. The substrates were 0.2-mm thick steel foil coated with 0.5-/spl mu/m thick SiO/sub 2/. We employed silicon crystallization times ranging from 6 h (600/spl deg/C) to 20 s (950/spl deg/C). Thin-film transistors (TFTs) were made in either self-aligned or nonself-aligned geometries. The gate dielectric was SiO/sub 2/ made by thermal oxidation or from deposited SiO/sub 2/. The field-effect mobilities reach 64 cm/sup 2//Vs for electrons and 22 cm/sup 2//Vs for holes. Complementary metal-oxide-silicon (CMOS) circuits were fabricated with self-aligned TFT geometries, and exhibit ring oscillator frequencies of 1 MHz. These results lay the groundwork for polycrystalline silicon circuitry on flexible substrates for large-area electronic backplanes.

Large-grain polycrystalline silicon films with low intragranular defect density by low-temperature solid-phase crystallization without underlying oxide

The solid-phase crystallization of an amorphous silicon film to polycrystalline silicon by a low-temperature (⩽600 °C) furnace anneal has been investigated in a suspended cantilever structure without underlying silicon oxide by transmission electron microscopy and Raman spectroscopy. The grain size of polysilicon increases up to ∼3.0 μm and the density of intragranular defects decreases one order of magnitude in the samples without underlying oxide, compared with those with underlying oxide. The main reasons for the high quality of the suspended structures are thought to be due to the lower stress in the films during crystallization and a reduced grain nucleation rate.

Nanopatterning of Si/SiGe electrical devices by atomic force microscopy oxidation

Two nanopatterning methods for silicon/silicon-germanium (Si/SiGe) heterostructures are demonstrated: (1) direct atomic force microscopy (AFM) oxidation on SiGe layers and (2) AFM oxidation on silicon followed by selective wet etching of SiGe. When directly oxidizing SiGe alloys, minimum linewidths of 20 nm were achieved by adjusting the bias voltage of the AFM tip. By AFM oxidation and selective wet etching, a 10-nm-thick conducting SiGe layer was patterned to form features under ∼50 nm. Fabricated SiGe quantum dots with side gates exhibited Coulomb blockade oscillation.

Spatially selective single-grain silicon films induced by hydrogen plasma seeding

The enhancement of a hydrogen plasma treatment on the solid-phase crystallization of hydrogenated amorphous silicon has been applied to form single crystalline silicon islands at designed locations. Holes with diameters from 0.4 to 1.8 μm were opened in silicon nitride, and then amorphous silicon films within the holes were exposed to a hydrogen plasma to create microcrystalline seeds. After furnace annealing, the relationship between the size of holes and number of grains in the holes has been investigated. It is found that a single nucleus cannot be induced until the diameter of holes decreases below 0.6 μm. Further annealing enlarges the grain size by lateral growth but does not increase the number of grains in the hole.

SiGe quantum dot single-hole transistor fabricated by atomic force microscope nanolithography and silicon epitaxial-regrowth

A SiGe quantum dot single-hole transistor passivated by silicon epitaxial regrowth with extremely stable Coulomb blockade oscillations has been demonstrated. The quantum dot was defined by atomic force microscopy nanopatterning technique and subsequently passivated by the epitaxial regrowth of silicon. Such passivation of the dot avoids any potential defect states on the dot associated with the Si∕SiO2 interface. Coulomb blockade oscillations controlled by side planar gating at ∼0.3K are reproducible, in sharp contrast with the noisy and irreproducible I-V characteristics of unpassivated SiGe quantum dot devices. An additional top gate was used to further tune the Coulomb blockade oscillations, enabling a shift in side-gate voltage of up to three periods.

SiGe single-hole transistor fabricated by AFM oxidation and epitaxial regrowth

In this paper, we report a new method for the fabrication of Si-based quantum dot devices with an all low-energy patterning process based on AFM lithography (to avoid defects from e-beam and RIE) and Si/SiGe heterojunctions with epitaxial regrowth to confine holes in three-dimensions. A single-hole transistor, which is the first reported SiGe quantum device with heterojunction passivation/carrier confinement, shows remarkably clean Coulomb blockade oscillations.

Silicon Epitaxial Regrowth Passivation of SiGe Nanostructures Pattered by AFM Oxidation

SiGe quantum devices were demonstrated by AFM oxidation and selective wet etching with features size down to 50 nm. To passivate the devices and eliminate the interface states between Si/SiO 2 , low temperature regrowth of epitaxial silicon over strained SiGe has been tested. The silicon regrowth on Si 0.8 Ge 0.2 was done by rapid thermal chemical vapor deposition (RTCVD) at 700 °C using a hydrogen pre-cleaning process at 800 °C and 10 torr. SIMS analysis and photoluminescence (PL) of strained SiGe capped with epitaxial regrown silicon show a clean interface. Nano-gaps between doped SiGe filled and overgrown with epitaxial silicon show an electrical insulating property at 4.2 K.

Si/SiGe Nanostructures Fabricated by Atomic Force Microscopy Oxidation

In this work, local AFM oxidation technique in a controlled humidity environment has been used to create small features in strained SiGe alloys. When directly oxidizing SiGe alloys, minimum line widths of 20nm were achieved by adjusting parameters such as the bias voltage on the microscope tip and the tip writing speed. It was found that when bias voltage increases, and/or when the tip writing speed decreases, the oxidation height of silicon-germanium increases. In contrast to conventional thermal oxidation, the oxide height on SiGe alloys is slightly less than that on Si. Finally, this method was used to successfully cut conducting SiGe quantum well lines with high resolution.