Haizhou Yin

Will SOI have a life for the low-power market?

We discuss key challenges for SOI CMOS to achieve sub-100 pA/m leakage current required for low-standby power applications. Recent 45 nm data is used to illustrate the importance of junction engineering to mitigate SOI floating body effect for low leakage design. With device scaling towards 22 nm node, both bulk and SOI technologies are expected to hit a fundamental GIDL limit. Extremely-thin body SOI provides a scaling path for low-leakage SOI. Finally, we identify several unique SOI opportunities that can broaden its appeal to the low power market.

High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond

This paper presents performance evaluation of high-κ/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45nm Poly/SiON devices. No additional stress elements were used for this performance gain. The critical path circuits of this low power microprocessor built with HK/MG show dynamic performance gain over 50% at same supply voltage and 36% lower dynamic energy at same performance. Superior SRAM minimum operating voltage characteristics are achieved due to Vt variability reduction from HK/MG. Analog circuit functionality is demonstrated by a fully integrated PLL circuitry without any modification to process.

35nm SOI-CMOS for Sub-Ambient Temperature Operation

We demonstrate over 40% CMOS performance gain with minimal process changes by lowering the operating temperature from 100degC to -50degC. For the same performance, the lower temperature operation delivers a 60% reduction in power-delay product at a reduced supply voltage. Coupled with recent advances in liquid cooling techniques, our results suggest that sub-ambient temperature operation is an attractive option for high performance and energy-efficient CMOS.

Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond

Scaling of CMOS logic devices from 45nm technology node has led tremendous challenges to 32nm node device integration to recover pitch-scaling induced performance deficit. In order to restore the performance shortage, it is prerequisite to integrate the best known technology enablement into the product with additive component. This paper provides a forum for reviewing and discussing new elements and challenges in the front end of line (FEOL) process integration for 32nm logic devices in the following areas: Metal/high(MHK) gate stack, mobility enhancement substrate technology and strain engineering.