Sheqin Dong

Corner block list: an effective and efficient topological representation of non-slicing floorplan

In this paper, a corner block list-a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block placement. Given a corner block list, it takes only linear time to construct the floorplan. Unlike the O-tree structure, which determines the exact floorplan based on given block sizes, corner block list defines the floorplan independent of the block sizes. Thus, the structure is better suited for floorplan optimization with various size configurations of each block. Based on this new structure and the simulated annealing technique, an efficient floorplan algorithm is given. Soft blocks and the aspect ratio of the chip are taken into account in the simulated annealing process. The experimental results demonstrate the algorithm is quite promising.

Interconnection driven VLSI module placement based on quadratic programming and considering congestion using LFF principles

In VLSI module placement interconnection behavior becomes increasingly important. Less flexibility first (LFF) principle is derived from human accumulated experience. An interconnection driven VLSI module placement algorithm based on LFF principles is proposed in this paper. We first use quadratic programming to optimize the total wire-length of the placement and then using a deterministic recursive partition rectangle packing algorithm based on LFF principles with consideration of congestion to implement the placement in an estimated fixed die area. Experimental results show efficiency and effectiveness of the proposed method.

UNISM: Unified Scheduling and Mapping for General Networks on Chip

Task scheduling and core mapping have a significant impact on the overall performance of network on chip (NOC). In this paper, a unified task scheduling and core mapping algorithm called UNISM is proposed for different NOC architectures including regular mesh, irregular mesh and custom networks. First, a unified model combining scheduling and mapping is introduced using mixed integer linear programming (MILP). Then, a novel graph model is proposed to consider the network irregularity and estimate communication energy and latency, since the number of network hops is not accurate enough for irregular mesh and custom networks. To make the MILP-based UNISM scalable, a heuristic is employed to speed up our method. Compared with two previous state-of-the-art works, experimental results show that more than 15% and 11.5% improvement on the execution time is achieved with similar energy consumption on average for regular mesh NOC. For irregular and custom NOC, the improvement is 27.3% and 14.5% on the execution time with 24.3% and 18.5% lower energy. Moreover, our method is scalable for large benchmarks in terms of runtime.

Corner block list representation and its application to floorplan optimization

We propose to use a corner block list (CBL) representation for mosaic floorplans. In a mosaic floorplan, each room has only one block assigned to it. Thus, there is a unique corner room on the top right corner of the chip. Corner block deletion and corner block insertion keep the floorplan mosaic. Through a recursive deletion process, a mosaic floorplan can be converted to a representation that is named as CBL. Given a CBL, it takes only linear time to construct the floorplan. The CBL is used for the application to very large-scale integration floorplan and building block placement. We adopt a simulated annealing process for the optimization. Soft blocks and the aspect ratio of the chip are taken into account in the optimization process. The experimental results demonstrate that the algorithm is quite promising.

Floorplanning and topology generation for application-specific network-on-chip

Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

ECBL: an extended corner block list with solution space including optimum placement

A Non-Slicing floorplanning algorithm based on CBL[1], corner block list, was presented recently. It can represent non-slicing floorplans without empty rooms. In this paper, we propose an extended corner block list structure, ECBLl, to represent general non-slicing floorplans, which may include empty rooms. By setting l×[1..3], where l is the extending ratio, our algorithm can translate a topological floorplan to its corresponding placement in O(n) time, where n is the number of blocks. Also, based on the optimum solution theorem of bounded-sliceline grid in [2], we proved that the solution space of ECBLn contains the optimum block placement, which has the minimum area. Experimental results on MCNC benchmarks show promising performance with 7% improvement in wire length and 2% decrease in dead space over algorithms based on CBL. Meanwhile, compared with other algorithms, our algorithm can get better results with less runtime.

Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit

A general algorithm for fitting arbitrary channel width transistors in a two-dimensional common centroid MOS transistor matrix is presented. The proposed algorithm guarantees the layout of the transistor unit-circuit not only to be complete common centroid, but also optimal in all the common centroid structures. A novel channel routing algorithm to implement common centroid routing is also proposed. Feasibility of the algorithm is demonstrated by practical analog transistor unit-circuits.

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs

Thermal issue is a critical challenge in 3D IC circuit design. Incorporating thermal vias into 3D IC is a promising way to mitigate thermal issues by lowering down the thermal resistances between device layers. However, it is usually difficult to get enough space at target regions to insert thermal vias. In this paper, we propose a novel analytical algorithm to re-allocate white space for 3D ICs to facilitate via insertion. Experimental results show that after reallocating whitespaces, thermal vias and total wirelength could be reduced by 14% and by 2%, respectively. It also shows that whitespace distribution with via planning alone will degrade performance by 9% while performance-aware via planning method can reduce thermal via number by 60% and the performance is kept nearly unchanged.

Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on corner block list

The abutment constraint problem is one of the common constraints in practice to favor the transmission of data between blocks. Based on Corner Block List(CBL), a new algorithm to deal with abutment constraints is developed in this paper. We can obtain the abutment information by scanning the intermediate solutions represented by CBL in linear time during the simulated annealing process and fix the CBL in case the constraints are violated. Based on this algorithm, a new method to deal with L-shaped/T-shaped blocks is proposed. The shape flexibility of the soft blocks and the rotation and reflection of L-shaped/T-shaped blocks are exploited to obtain a tight packing. The experiment results are demonstrated by some benchmark data and the performance shows effectiveness of the proposed method.

VLSI floorplanning with boundary constraints based on corner block list

In floorplanning of typical VLSI design, some modules are required to satisfy some placement constraints in the final packing. Boudary Constraint is one kind of those placement constraints to pack some modules along one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. We implement the boundary constraint algorithm for general floorplan by extending the Corner Block List (CBL) - a new efficient topology representation for non-slicing floorplan. Our contribution is to find the necessary and sufficient characterization of the modules along the boundary represented by Corner Block List. So that we can check the boundary constraints by scanning the intermediate solutions in the linear time during the simulated annealing process and fix the corner block list in case the constraints are violated. The experiment results are demonstrated by several examples of MCNC benchmarks and the performance is remarkable.