Xiao-Dong Deng

340 GHz On-Chip 3-D Antenna With 10 dBi Gain and 80% Radiation Efficiency

This paper discusses the design methodologies of a 340 GHz on-chip 3-D antenna. Firstly, a high-gain and high-radiation efficiency substrate integrated waveguide (SIW) cavity backed on-chip antenna is designed using a standard 0.13- μm SiGe BiCMOS technology. Then, a low-permittivity supporter and a dielectric resonator (DR) are vertically stacked on the proposed on-chip antenna, forming a 3-D Yagi-like antenna to further enhance the gain and radiation efficiency. The measurements showed that the proposed antenna achieved a peak gain of ~10 dBi and radiation efficiency of ~80% at 340 GHz; the impedance bandwidth is ~12% with the use of dielectric resonator antenna (DRA) and the Yagi-like structure. The antenna size is ~0.7×0.7 mm2.

A 320-GHz 1

This paper presents a 320-GHz 1 ×4 fully integrated phased array transmitter using 0.13- μm SiGe BiCMOS technology. The 1 ×4 array transmitter is aiming for terahertz wireless communication and is based on RF beam forming architecture. By integrating a 20-GHz phase-locked-loop (PLL) frequency synthesizer, an 80-GHz quadrupler, a 1:4 Wilkinson power divider network, four-way 80-GHz tunable attenuators, amplifiers, analog phase shifters, 320-GHz frequency quadruplers/modulators, and on-chip antenna arrays, the transmitter chip achieves a maximal EIRP of 10.6 dBm at 320 GHz with the 3-dB bandwidth of 20 GHz, and ± 12° beam scanning range is obtained. The dc consumption of the whole chip is ~ 1000 mW and the total chip size is 8 × 4.3 mm 2 .

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This paper presents an chip-to-waveguide-horn (CWH) antenna structure to improve silicon-based on-chip antenna gain at D-band. In the proposed CWH antenna structure, a transition from chip to rectangular waveguide is adopted and is followed by a horn for power radiation. For the chip-to-waveguide transition, a high efficiency dielectric resonator antenna (DRA), which is excited by a substrate integrated waveguide (SIW) cavity backed on-chip antenna, is used to transfer the power to the waveguide. The simulated results indicate 45% radiation efficiency and -17 dB reflection coefficient for the CWH antenna at 140 GHz. The proposed CWH antenna is measured by using on-wafer testing method and the measured results show the peak gain of 18.9 dBi at 143 GHz with the 3 dB bandwidth of 21 GHz and the reflection coefficients <;-6 dB from 120-160 GHz.

4 Fully Integrated Phased Array Transmitter Using 0.13-

A 340-GHz on-chip antenna (OCA) with highgain and high-radiation efficiency is designed using a standard 0.13-μm SiGe BiCMOS technology without any postprocesses. In the proposed OCA structure, a rectangular slot loop is etched in the upper wall of a substrate integrated waveguide (SIW) to form a magnetic current loop radiator. The SIW structure forms a back cavity to suppress the surface waves and separate the radiation aperture from the low-resistivity substrate. Furthermore, the side wall of the SIW cavity and the edge of the slot form a λg/4 resonator to reflect the power back to the slot loop. As a result, the radiation efficiency is improved. By etching a slot properly in the SIW upper wall, another resonating point is constructed and hence, the bandwidth is broadened. Single antenna element and a 2 × 2 array are both designed and fabricated withand withoutthe slot structure; a maximum gain of 7.9 dBi with the radiation efficiency of 48% at 340 GHz is achieved for the proposed SIW cavity-backed antenna structure.

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This paper presents a reflection-type phase shifter (RTPS) at W-band in a 0.13 µm complementary metal oxide semiconductor (CMOS) process. The RTPS is composed of a 90° hybrid coupler and two identical reflection loads. Lumped-distributed element transmission line is introduced in the 90° hybrid coupler to reduce the chip size. Series inductor-capacitor (LC) resonators are used as the reflective loads and parallel inductors are deployed to reduce insertion loss variation. By cascading two-stage RTPS, 90° phase shifting range and 10.5 dB insertion loss with 1 dB variations from 80 GHz to 90 GHz are achieved. An impressive 0.1 dB variation is obtained at 86 GHz.

m SiGe BiCMOS Technology

This paper presents a 340 GHz 4-way fully integrated phased array transmitter using 0.13um SiGe BiCMOS technology. The chip integrates a 21.25 GHz synthesizer, a quadrupler together with a 1:4 Wilkinson network, power amplifiers, analog phase shifters, 20Gbps OOK modulators, and 2×2 on-chip antenna arrays on each channel. Simulated patterns show scanning to ±12° and >12dBi gain in E-plane. The chip size of the fully integrated phased array transmitter is 8×4.3 mm2.

A D-band chip-to-waveguide-horn (CWH) antenna with 18.9 dBi gain using CMOS technology

This paper presents a D-band down conversion chipset using 0.13μm SiGe BiCMOS technology. The chipset consists of a 62.5GHz doubler and a 2nd sub-harmonic mixer (2× SHM) with I-Q outputs. The doubler uses a push-push topology. The 2× SHM uses SiGe HBT to form a cascode structure and followed with a source follower. The output 62.5GHz signal of the doubler is split into two ways by Wilkinson power divider: one way is fed to a 2× SHM directly, while the other way is fed to a 2× SHM after 45° phase shifting by microstrip line, thus the IF with I-Q output is achieved. The chip size is 1.6×0.85 mm2. The measurement results show that the peak conversion gain is 0.8dB with RF @137GHz (IF@12GHz) and LO @ 31.25GHz and the difference between I/Q output is less than 1 dB with the IF frequency 3-18 GHz.

340-GHz SIW Cavity-Backed Magnetic Rectangular Slot Loop Antennas and Arrays in Silicon Technology

In this paper, the characteristics of on-chip rectangular coaxial line (RCL) are analyzed and a single-pole single-throw (SPST) switch is demonstrated utilizing the RCL in a standard 0.13-μm CMOS technology. The characteristic impedance of the RCL is promoted to 20-54Ω range, which makes it convenient to design a 90° hybrid coupler. A SPST switch at W-band is designed utilizing the coupler and the measured results indicate that the insertion loss is ~3.8 dB and the isolation is better than 11 dB from 85 to 100 GHz with the peak value of 20.1dB at 94 GHz. The chip size is 0.26×0.26 mm2 excluding the testing pads.