Yihu Li

Atomic layer deposition of ZrO2 as gate dielectrics for AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors on silicon

In this Letter, the device performance of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MISHEMTs) on silicon substrate using 10-nm-thick atomic-layer-deposited ZrO2 as gate dielectrics is reported. The ZrO2 AlGaN/GaN MISHEMTs showed improved maximum drain current density (Idmax) with high peak transconductance (gmmax) as comparison to Schottky-barrier-gate HEMTs (SB-HEMTs). Also compared to SB-HEMTs, reverse gate leakage current was four orders of magnitude lower and forward gate bias extended to +7.4 V. At energy from −0.29 eV to −0.36 eV, low interface trap state density evaluated by AC conductance and “Hi-Lo frequency” methods indicates good quality of atomic-layer-deposited ZrO2 dielectric layer.

Si Nanopillar Array Surface-Textured Thin-Film Solar Cell With Radial p-n Junction

The electrical characteristics of a Si nanopillar array surface-textured thin-film solar cell with radial p-n junction are studied in this letter. Several key factors affecting the power conversion efficiency (PCE) of the solar cell, e.g., surface recombination velocity, the shell thickness, back surface field, and minority carrier diffusion length, are highlighted. The radial p-n junction provides better PCE than the axial p-n junction at same given conditions (i.e., doping concentration, minority carrier diffusion length, etc.), indicating that the radial p-n junction is preferred in improving the cells performance.

340 GHz On-Chip 3-D Antenna With 10 dBi Gain and 80% Radiation Efficiency

This paper discusses the design methodologies of a 340 GHz on-chip 3-D antenna. Firstly, a high-gain and high-radiation efficiency substrate integrated waveguide (SIW) cavity backed on-chip antenna is designed using a standard 0.13- μm SiGe BiCMOS technology. Then, a low-permittivity supporter and a dielectric resonator (DR) are vertically stacked on the proposed on-chip antenna, forming a 3-D Yagi-like antenna to further enhance the gain and radiation efficiency. The measurements showed that the proposed antenna achieved a peak gain of ~10 dBi and radiation efficiency of ~80% at 340 GHz; the impedance bandwidth is ~12% with the use of dielectric resonator antenna (DRA) and the Yagi-like structure. The antenna size is ~0.7×0.7 mm2.

A 320-GHz 1

This paper presents a 320-GHz 1 ×4 fully integrated phased array transmitter using 0.13- μm SiGe BiCMOS technology. The 1 ×4 array transmitter is aiming for terahertz wireless communication and is based on RF beam forming architecture. By integrating a 20-GHz phase-locked-loop (PLL) frequency synthesizer, an 80-GHz quadrupler, a 1:4 Wilkinson power divider network, four-way 80-GHz tunable attenuators, amplifiers, analog phase shifters, 320-GHz frequency quadruplers/modulators, and on-chip antenna arrays, the transmitter chip achieves a maximal EIRP of 10.6 dBm at 320 GHz with the 3-dB bandwidth of 20 GHz, and ± 12° beam scanning range is obtained. The dc consumption of the whole chip is ~ 1000 mW and the total chip size is 8 × 4.3 mm 2 .

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This paper presents an chip-to-waveguide-horn (CWH) antenna structure to improve silicon-based on-chip antenna gain at D-band. In the proposed CWH antenna structure, a transition from chip to rectangular waveguide is adopted and is followed by a horn for power radiation. For the chip-to-waveguide transition, a high efficiency dielectric resonator antenna (DRA), which is excited by a substrate integrated waveguide (SIW) cavity backed on-chip antenna, is used to transfer the power to the waveguide. The simulated results indicate 45% radiation efficiency and -17 dB reflection coefficient for the CWH antenna at 140 GHz. The proposed CWH antenna is measured by using on-wafer testing method and the measured results show the peak gain of 18.9 dBi at 143 GHz with the 3 dB bandwidth of 21 GHz and the reflection coefficients <;-6 dB from 120-160 GHz.

4 Fully Integrated Phased Array Transmitter Using 0.13-

A sub-terahertz frequency doubler with signal modulation is proposed and analyzed in this letter. An 85 GHz input signal is modulated by a differential pair, and a push-push frequency doubler with capacitive degeneration technique is designed to obtain the 170 GHz modulated output signal. Via the use of negative impedance to eliminate the leakage current of transistors, the proposed enhanced push-push frequency doubler achieves a power efficiency of 8.5% and a maximum output power of 4.5 dBm at 170 GHz without applying a modulation signal. The 0.13 μm SiGe BiCMOS process is used to fabricate the proposed design and the total chip area is 0.75 × 0.8 mm2.

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A cascade distributed amplifier (DA) is designed and analyzed in this letter. The proposed DA is fabricated in 0.13 μm SiGe HBTs process and patterned ground micro-strips are deployed for the design of distributed inductors to achieve high-Q in the transmission line (TL). In addition, negative resistors and capacitors are used to widen the bandwidth. Gain boosting techniques are also used to ensure gain flatness throughout the band. The fabricated DA achieves an average gain of 17.5 dB and 14.5 dB gain at 110 GHz. 7.5 and 2.7 dBm saturated output power are obtained at 50 and 100 GHz, respectively. The total chip size is 0.8 mm × 1.8 mm, including the bond pads.

m SiGe BiCMOS Technology

This paper presents a 324-GHz signal source/transmitter. Input signal of 81 GHz is applied to a differential pair for conversion to 324 GHz via two cascaded push-push frequency doublers. Stacked push-push configuration is used for enhancing the output power at 324 GHz and passive baluns with asymmetrical grounding stub is deployed to improve the power efficiency. The 81-GHz signal can correspondingly be modulated to function as a modulator. The proposed design is fabricated using 0.13- μm SiGe BiCMOS process. The total chip area is 0.95 mm ×1 mm. With the buffers, the total DC consumption is 42.5 mW. The maximum output power is -6.5 dBm at 324 GHz when the input power of the 81-GHz signal is of 0 dBm. The ability to transmit modulated signals has also been demonstrated in the proposed circuit.

A D-band chip-to-waveguide-horn (CWH) antenna with 18.9 dBi gain using CMOS technology

An ultra-broadband mixer with I-Q outputs is proposed and analyzed in this paper. The mixer is composed of a distributed amplifier, a traveling wave power splitter and two active mixers where the input capacitors are absorbed in the artificial transmission lines. The orthogonal LO inputs are fed to the mixers via an on-chip Lange coupler. With the aid of loss compensation techniques, the proposed mixer can operate up to 110 GHz. An average conversion gain of 5.5 dB/14.5 dB is achieved with 1 dBm LO input power without/with the pre-distributed amplifier, respectively. 0.13- μm SiGe process is used to fabricate the proposed design. Including the testing pads, the total chip areas both without and with the pre-distributed amplifier are (1.2 ×1) mm2 and (2 ×1) mm2, respectively.

A Frequency Doubler/Modulator With 4.5 dBm Output Power at 170 GHz Using SiGe HBTs

This paper presents a broad band distributed amplifier (DA). The amplifying cell utilizes the cascode structure with transistor dimension mismatch. With different sizes of the transistor used, the input and output capacitance will be more balanced and hence, better impedance matching is achieved for the designed DA. 70 nm InP HEMTs are used to fabricate the proposed design, the total chip area occupied is 2.9mm×0.85mm including the bonding pads. The DA achieves a band width of 2 to 82 GHz, with the average gain of 21 dB. The total power consumption of the DA is 300 mW with a power supply voltage of 2 V.