Xiao Xindong

An optical receiver with automatic gain control for radio-over-fiber system

An optical receiver circuit with automatic gain control (AGC) for radio-over-fiber (RoF) system is presented. The AGC optical receiver is designed on the standard 0.18µm CMOS technology. The proposed circuit uses a differential variable gain amplifier (VGA), implemented by a Gilbert cell and provides an exponential function circuit for the dB linearity of the gain voltage. A large dynamic range of the receiver is from 13dB to 75dB. The AGC loop bandwidth is 3.3GHz, with a power consumption of 101mW and a low noise current of 1.45µA, and the eye diagram of the receiver is also good.

A differential automatic gain control circuit with two-stage −10 to 50 dB tuning range VGAs

A differential automatic gain control (AGC) circuit is presented. The AGC architecture contains two-stage variable gain amplifiers (VGAs) which are implemented with a Gilbert cell, a peak detector (PD), a low pass filter, an operational amplifier, and two voltage to current (V—I) convertors. One stage VGA achieves 30 dB gain due to the use of active load. The AGC circuit is implemented in UMC 0.18-μm single-poly six-metal CMOS process technology. Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp; the total gain of the two VGAs can be varied linearly from −10 to 50 dB when the control voltage varies from 0.3 to 0.9 V. The final circuit (containing output buffers and a band-gap reference) consumes 37 mA from single 1.8 V voltage supply. For a 50 mV amplitude 60% modulation depth input AM signal it needs 100 μs to stabilize the output. The frequency response of the circuit has almost a constant −3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.

An Automatic Gain Control Circuit for a Single-Chip UHF RFID Reader Transceiver

This paper presents an automatic gain control (AGC) circuit which is used in a single-chip UHF RFID reader transceiver system. The VGA is a fully differential circuit with differential output swing of 1-Vpp. The gain of the two VGAs can be varied linearly from 0dB to 60dB with respect to a control voltage from 0.28V to 0.93V. The exponential voltage to current (V-I) convertor is based on Taylor’s series expansion. The AGC circuit consumes 4.5mA current and has a 2.7MHz 3-dB bandwidth when the gain is 60dB. A differential positive peak detector is used in the AGC circuit loop. The AGC circuit is based on UMC 0.18-μm single-poly six-metal CMOS process technology.

A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic integrated receiver based on a metal–semiconductor–metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photogenerated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM photodetectors low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to –3 dB frequency.

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10−9. The chip dissipates 60 mW under a single 3.3 V supply.

An approach to the optical interconnect made in standard CMOS process

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.