Xiaojing Su

New alignment mark design structures for higher diffraction order wafer quality enhancement

ASML AH53 and AH74 with higher odd-order diffraction light are the widely used alignment marks in industry to achieve better alignment accuracy by reducing mark damage noise. During lithography alignment process, decent diffraction light power is the basic demand. However, with the use of some high absorption (k is not equal to 0 for detective wavelength) material, it is difficult to detect the light power reflecting from the thick and opaque film stacks with these standard alignment marks. Here we optimized four alignment marks with higher odd-order diffraction power with comparing with AH53 and AH74. One software based on Fourier optical theory is built to quickly calculate the wafer quality (WQ) of different film stacks and different alignment marks. ASML SMASH alignment system can accept customized alignment mark, with new mark type configuration file. In order to demonstrate the effectiveness of new alignment marks, we put the marks on a mask and do the experiments to compare with simulation results. All the experiments results show that new designed alignment marks have larger WQs of odd-order diffraction.

Characteristic study of image-based alignment for increasing accuracy in lithography application

Image-based overlay and alignment is an effective technology for finding wafer positions precisely. Methods to increase the alignment accuracy and decrease the alignment tolerance for the lithography application are important and challenging, which need more study to consider the problems in a broader context. In view of this, the inner characteristics of image-based alignment are investigated in this paper by studying the case with phase difference only as well as the case with both power and phase differences. Based on the study, the authors propose some recommendable conclusions. For the case with phase difference only, the mark period should be about four times of optical spot size, the light spot size needs to be minimized for higher resolution, and the subwavelength alignment mark is not recommended to use due to its larger cross-correlation curve width. By contrast, for the case that both power and phase differences exist in application, subwavelength property has great advantages in choosing the b...

Design technology co-optimization for N14 Metal1 layer

Design and technology co-optimization (DTCO) is a new technology method, which takes the manufacturing process limitations, mainly lithography, into account during the early design stage. This paper demonstrates a DTCO workflow which includes layout generation, pattern analysis, hotspot library establishment and design rule optimization mainly. And the paper also gives an example about the method to optimize the design rule related to SADP decomposition. The DTCO workflow can generate friendly layout and find the hotspot patterns in order to avoid the unfriendly design in the advance work and make sure that the layout can be manufactured by the current process level. The DTCO workflow proposed in this paper is an efficient solution for refining the design rules for 14/10 nm tech node Metal1 layer.

Optimization of resist parameters to improve the profile and process window of the contact pattern in advanced node

Abstract. Typically, the printing of contact patterns uses a dark-field (DF) mask in combination with a positive tone resist and positive tone development (PTD) process. PTD, which has a mature process and simulation model, had been widely applied in high-volume manufacturing. For the low aerial image quality of a DF mask in advanced node, PTD is substituted by negative tone development (NTD), which uses a positive tone resist and bright-field mask. Due to the high cost and immature simulation model of NTD process, it is worthwhile to extend PTD to some critical patterns. With the purpose of improving the resist profile and process window (PW) of the contact pattern with a PTD process in advanced node, an optimization method combined with the idea of a genetic algorithm is put forward. For performance of the optimized resist under the conditions of best focus and best dose, an evaluation based on the through pitch square contact patterns with the critical dimension (CD) fixed at 50 nm has been provided. The generalization performance of the optimized resist is also analyzed by a systematic method, which contains the resist profile and PW simulation on the base of through CD and through pitch contact patterns. The above simulation results verify the effectiveness and validity of the proposed optimization method.

Pattern quality and defect evaluation based on cross correlation and power spectral density methods

Precise detection of a nanometer-scale patterns edge positions in an SEM image is challenging for next generation patterning technology development. Here, two different edge detection methods are proposed: one is based on a normal method employing the edge threshold algorithm and the other is based on a cross-correlation method by calculating the real image with a reference. Line/space and circle pattern types are both studied and compared with the two methods. By using different SEM images without noise and with noise, the pros and cons of the abovementioned two methods are summarized. With the implementation of the power spectral density method, the comparison shows that the cross-correlation method suppresses the metrology uncertainty of edge positions and edge roughness. Besides, the cross-correlation method also calculates all potential edge defects, especially the footing defects and the top loss defects. The method has high application potential in the 3D reconstruction process by using different ...

Hybrid hotspot library building based on optical and geometry analysis at early stage for new node development

As the semiconductor industry enters 20 nm node and beyond, design restrictions and process complexity lay stress on the development for a new technology node. This paper introduces a hybrid hotspot library building method based on simultaneous optical and geometry analysis, which could help explore design rule optimization and enhance cycle time at early stage for new node development. Lithography simulation results verify the accuracy of this method. This method provide a feasible way to build up a preliminary Design Rule Checking (DRC) library even before process-freezing.

An offline roughness evaluation software and its application in quantitative calculation of wiggling based on low frequency Power Spectral Density method

It is greatly important to accurately characterize the critical dimension (CD) and the roughness of line patterns in advanced lithography and etch process. Thus we wrote an offline roughness evaluation software and did lots of relevant researches. Two different edge finding algorithms are compared to reduce the CD uniformity. Power Spectral Density (PSD) algorithm is used to analyze the LER and LWR. Palasantzas function is used for fitting the PSD data and giving three important parameters. Such software could evaluate the line wiggling in practical applications. The origin of line wiggling and qualitative methods based on low frequency PSD is studied. With the help of the models and algorithms, we can figure out the existence and strength of wiggling for a SEM image.

Enhancing manufacturability of standard cells by using DTCO methodology

We demonstrate two different approaches of implementing design technology co-optimization (DTCO). One is on optimizing standard cells. Before being placed on mask, standard cells can be evaluated and optimized to gain better process windows. This approach enables an additional learning cycle before mask tapeout, reducing process development cost. The other approach uses a random pattern generator to create various patterns with high coverage based on given design rules. Lithography simulation is used to evaluate process window of these patterns, and annotates its printability. Test patterns generated in this way can be used for early process development.

Hotspots fixing flow in NTD process by using DTCO methodology at 10nm metal 1 layer

This paper proposes a novel hotspots fixing flow, in which design rule optimization and lithography RET solution are obtained simultaneously. This flow is most effective in the early development phase, and its methodology is rooted from design technology co-optimization (DTCO). Two layout files, corresponding to separate colors of a double-pattern layer (10nm node M1), are first generated by a pattern generator, and they meet no-stitching requirements and are design rule check (DRC) clean. Then, source, mask and design rule co-optimization is done with the layouts, and the design rules are optimized to remove hotspots and enable maximum lithography process window (PW). The mask optimization (MO) in combination with cost function manipulation and design rule optimization improve the robustness of initial design rule. The application of the methodology illustrates a friendly design rule and avoids later design rework.

Improving the topography performance of ion implantation resist

As the fin based field effect transistors (Fin-FET) emerge, the device structure is changed from two dimensional to three dimensional. Due to the existence of topography, the lithographic performance may be affected and, in most cases, becomes more complicated, especially in the ion implantation process after gate being constructed. In this paper, the various parameters that may have influence on the resist topography are being investigated, such as the density, height, and corner rounding of the fin structures, the height, and the corner rounding of the gates, etc. Theoretical analysis shows that the resist image intensity among the fins and gates can be improved by increasing the thickness of the oxide on the edge of the gate. Following the above theoretical analysis, a method for lithographic performance improvement with the existence of resist topography is proposed. The method is demonstrated from the simulations with the lithography simulator PROLITH. With an optimal thickness of oxide on the surface of gate, the residual resist in the topography after development will be removed thoroughly. Compared with other methods, the proposed method requires neither a specific system setup nor an additional etch process, which is a tremendous cost-saving in mass production.