Xiaolang Yan

A Low-dropout Regulator with Unconditional Stability and Low Quiescent Current

An unconditionally stable low-dropout regulator (LDO) with ultra low quiescent current is presented. By using frequency compensation of dynamic miller on the LDOs structure, the proposed LDOs stability is independent of the load or off-chip capacitor. The LDO works at a low quiescent current of approximately 4 muA. Low quiescent current is due to a precision CMOS current reference, which operates in subthreshold region and generates 30 nA bias current. The current reference has max-to-min fluctuation of less than 2.5% over a temperature range of -40 degC to 150 degC. The proposed LDO has been implemented in a 0.5-mum CMOS technology. The experimental results revealed that the LDO provides a full load transient response of less than 50 mus setting time and less than 75 mV overshoots and undershoots. Moreover, the dropout voltage is 170 mV at 150 mA loading, and quiescent current is 4.17 muA when output current is 150 mA

A Programmable Bitstream Parser for Multiple Video Coding Standards

Bitstream parsing is a basic task in video decoding systems. With the development of video compression standards, the trend of the VLSI architecture for bitstream parser is toward programmable. Due to the strong data-dependency and bit-level sequential operations, bitstream parsing is unsuitable to accelerate by general architectures, such as RISC, SIMD and VLIW processors. This paper proposes a programmable bitstream parser for multiple video coding standards on embedded RISC processors. The proposed design presents an extension instruction set to accelerate some kernel functions of bitstream parsing. As a result, the proposed bitstream parser can decode every syntax element per cycle. The synthesis result shows that at the clock constraint of 150MHz, the hardware cost is about 7K gates of logic and 2k byte RAM under a 0.1 mu;m CMOS technology

A Current-Mode DC-DC Buck Converter with High Stability Independent of Load and Supply Voltage

A current-mode DC-DC buck converter with high stability independent of load and supply voltage is presented. The loop gains expression of the current-mode converter is derived by employing an advanced model of current-mode control converter. After analyzing the loop gains expression, which illustrates the method of selecting suitable frequency compensation for control-loop, and a novel pole-zero tracking frequency compensation is proposed. Based on theoretic analysis, a DC-DC buck converter which has high stability independent of load and supply voltage is designed with 0.5 mum-CMOS technology. The simulated results revealed that stability of the converter is independent of load current and input voltage. Moreover, the converter provides a full load transient response of less than 5 mus setting time and less than 30 mV overshoots and undershoots

Design and implementation of a high-speed and area-efficient viterbi decoder

A high-speed and area-efficient Viterbi decoder is presented in the paper, and a new survivor path structure including RAM blocks and trace-back decode circuit is proposed. The survivor path memory is consist of 4 single-port RAM blocks, which reduces the chips area comparing to the dual-port RAM structure; and a simple trace-back decoder circuit is implemented to get high speed. Only 2300 LEs are used in the Altera Stratix FPGA device to implement this design, and its speed is up to 163 MHz. The proposed Viterbi decoder can be introduced to the digital communication systems that need high speed such as DTV or HDTV broadcast

A simplified model of delta-distortion for JPEG2000 rate control

Rate-distortion optimized rate control is one of the superior features of JPEG2000. The calculation of delta-distortion for each pass is the key to implementing rate control. The paper presents a simplified model of delta-distortion calculation. Compared with the one in the verification mode (VM) of the JPEG2000 standard, this model has the following merits: code-block memory access free; lower memory requirement; lower computational complexity; less negative impact on image quality.

Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test array

Addressable test array needs switches to select and isolate testing structures; however, switches occupy extra chip area and limit the array size and measurement accuracy due to additional switch leakage. In this paper, we implement the switch by NMOS transistor, thus improve the design of addressable test array on array size, measurement accuracy as well as area efficiency. Simulations in a 65 nm technology have verified this techniques feasibility and reliability. A large 64×64 array using this 65 nm technology has been designed in a systematic flow and manufactured for silicon data, which further confirms the effectiveness of the presented technique.

A high efficient memory architecture for H.264/AVC motion compensation

In H.264/AVC decoding system, motion compensation operation occupies about 80% of the total memory access and becomes the system bottleneck. In this paper, a high efficient memory architecture for H.264/AVC motion compensation is proposed to extremely reduce external memory access bandwidth. A four-level hierarchical memory organization scheme is utilized to explore the reusability of neighboring blocks at an acceptable area cost. To improve the system processing throughput, five optimization techniques are adopted in motion compensation operation, which enable video decoder to achieve real-time decoding of HD 1080p video stream when operating at 110 MHz. Compared with the existing works, the proposed architecture is able to reduce the memory bandwidth requirement in motion compensation progress by 83.7% and performs better in the real-time application.

A feasible model-based OPC algorithm using Jacobian matrix of intensity distribution functions

The correction accuracy of a model-based OPC (MB-OPC) depends critically on its edge offset calculation scheme. In a normal MB-OPC algorithm, only the impact of the current edge is considered in calculating each edge offset. As the k1 process factor decreases and design complexity increases, however, the interaction between the edge segments becomes much larger. As a result, the normal MB-OPC algorithm may not always converge or converge slowly. Controlling the EPE is thus become harder. To address this issue, a new kind of MB-OPC algorithm based on MEEF matrix was introduced which is also called matrix OPC. In this paper, a variant of such matrix OPC algorithm is proposed which is suitable for kernel-based lithography models. Comparing with that based on MEEF matrix, this algorithm requires less computation in matrix construction. Sparsity control scheme and RT reuse scheme are also used to make the correction speed be close to a normal one while keeping its advantages on EPE control.

Architecture of a post-OPC silicon verification tool

With the wider usages of OPC and PSM technologies in current UDSM IC manufacturing, a new step of verifying the layout modifications is needed. Reasons to employ such a step are discussed in this paper. The architecture of a post-OPC silicon verification tool which has the full capability to accomplish such a verification task is presented in detail. Process modelling and some accelerating algorithms implemented in this tool are detailed as well. Real verification examples are also demonstrated.With the wider usages of OPC and PSM technologies in current UDSM IC manufacturing, a new step of verifying the layout modifications is needed. Reasons to employ such a step are discussed in this paper. The architecture of a post-OPC silicon verification tool which has the full capability to accomplish such a verification task is presented in detail. Process modelling and some accelerating algorithms implemented in this tool are detailed as well. Real verification examples are also demonstrated.

Efficient Reference Picture Management Schemes for H.264/AVC Decoding System

Inter-frame prediction with multiple reference pictures is one of the several advanced techniques in H.264/AVC standard. However, it also brings high implementation complexity. In this paper, we present two effective schemes and DPB storage arrangement for efficient reference picture management. One scheme is for direct mapping between reference picture index and DPB picture index and another scheme is to replace refidx of co-located block with its dpbidx in temporal direct prediction mode. These two schemes are utilized to optimize motion vector generation and reference block access, two kernel functions of inter-frame prediction. Experimental results show that the proposed schemes are able to reduce CPU workload by 80% and improve system throughput performance by 22.1%. Both schemes help our implemented decoder achieve real-time decoding of 1080p main profile H.264 video stream with 110 MHz clock frequency at the hardware cost of 53k and 37k gates for MC and MVPG modules respectively.