Chunshu Li

Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers

The ever improving cost advantages and processing capabilities of the technology have been happening according to the so-called Moore’s Law. Although digital circuits can significantly benefit from the aggressive scaling, it is very controversial for analog circuit. However, analog circuit still has to follow the scaling trend because a single chip integration offers key commercial advantages. To optimally achieve the best performance/power/cost tradeoff with deeply scaled technology nodes, there is a clear trend and paradigm shift towards digital intensive and digitally assisted transceivers. Successes of such transceivers have been proven for individual transceiver components and narrow band systems. When targeting emerging communication standards, higher carrier frequencies, further technology scaling and reconfigurable radios, required signal processing design and implementation are orders of magnitudes more challenging but potential gains are promising. Based on a variety of transceiver designs implementing emerging architectures for different sub-6 GHz and 60 GHz communication systems, we will highlight the key challenges and opportunities experienced using 40 nm and 28 nm technology nodes.

<30 mW rectangular-to-polar conversion processor in 802.11ad polar transmitter

This paper presents an energy-efficient digital signal processor (DSP) for rectangular-to-polar conversion in 802.11ad polar transmitter working on 60 GHz band. Firstly, system simulations with a complete transmission chain are conducted with regard to error vector magnitude and output spectrum, which allows to systematically optimize the design requirements on the DSP block. Secondly, algorithm and architecture co-optimization on the DSP block is explored to minimize the power consumption. Finally, the proposed DSP is synthesized using 28 nm CMOS technology, which provides a throughput of 7.04 Giga samples per second with a power consumption of 28 mW, and area of 0.01 mm2.

Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications

Aggressive power supply voltage Vdd scaling is widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical Vdd results to numerous setup timing errors, and hence to an unacceptable output quality. In this paper, we propose computation-skip (CS) scheme to mitigate setup timing errors, for recursive digital signal processors with a fixed cycles per instruction (CPI). A coordinate rotation digital computer (CORDIC) with the proposed CS scheme still functions when scaling beyond the error-free voltage. It enables better-than-worst-case design constraint and achieves 1.82 X energy saving w.r.t. nominal Vdd condition, another 1.49 X energy saving without quality degradation, and another 1.09 X energy saving when sacrificing 8.35 dB output quality.

Reduced Complexity On-chip IQ-Imbalance Self-Calibration

The architectural simplicity of the direct-conversion scheme makes it an appealing architecture for low cost and low power transceivers. This architecture however demonstrates increased sensitivity to analog front-end impairments, such as gain and phase imbalance in the transceivers in-phase and quadrature (IQ) paths. Especially when used in flexible software-defined radios, very fast, but low cost IQ-imbalance estimation and correction methods are required, to cope with the dynamically varying IQ imbalance due to environmental effect and frequency shifts. The main goal of this paper is to present an on-chip, off-line, extremely fast and low complexity self-calibration of IQ imbalance and carrier feed through for both the transmitter and receiver. Custom-designed training symbols allow to reduce the computational complexity, such that the calibration method can be performed at any user defined instance in negligible time. The reported complexity analysis shows that the whole calibration process takes up less than 4000 processor cycles, or 16us, when running on an OPENRISC 1200 core.

Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited)

Mainstream foundries are leaping toward 14nm node and beyond. Although aggressive scaling can substantially improve digital circuit, it is very controversial for analog circuit. However, analog circuit still has to follow the scaling trend because a single chip integration offers key commercial advantages. To optimally achieve the best performance/power/cost tradeoff with deeply scaled technology nodes, there is a clear trend and paradigm shift towards digital intensive and digitally assisted transceivers. Successes of such transceivers have been proven for individual transceiver components and narrow band systems. When targeting emerging communication standards, higher carrier frequencies, further technology scaling and reconfigurable radios, required signal processing design and implementation are orders of magnitudes more challenging but potential gains are promising. Illustrated with a variety of transceivers representing emerging architectures designed for different sub-6GHz and 60GHz communication systems, we will depict key challenges that we experienced in our design and optimization process with 40nm and 28nm technology nodes.

Efficient self-correction scheme for static non-idealities in nano-scale quadrature digital RF transmitters

As a disruptive solution exploiting the intrinsic speed of deeply scaled CMOS technology, digital RF transmitter has attracted extensive attention for its capability to handle multiple radio standards. However, deeply scaled nano level technology has both pros and cons, so that state-of-the-art designs still suffer from the combination of a large number of non-idealities that are inherent in deeply scaled technology. In this paper, a solution is proposed for the first time to tackle major static non-idealities simultaneously in digital RF transmitter employing an ultra-high-bandwidth digital-to-analog converter. Whereas existing work focuses on only correcting one or few non-idealities in isolated ways. The proposed input-signal segmentation and polynomial transforming scheme makes the proposal a computational efficient solution. Simulation combined with lab measurement results show that, after applying the proposed non-linearity self-correction scheme, on average, the root-mean-square error of a 28-nm digital RF transmitter output can be reduced by over 20 dB.

Efficient Timing Mismatch Correction for Low-Cost Digital-Mixing Transmitter

In this paper we present a novel digital predistortion method to eliminate the nonlinear timing mismatches, delay mismatch and duty cycle mismatch, in the in-phase and quadrature upconversion signals of a power-efficient digital transmitter architecture. This transmitter architecture has a separate digital-mixing stage before the digital-to-analog conversion, which halves the number of required current cells in the radio frequency digital-to-analog converter (RFDAC), but introduces a nonlinear performance impact of timing mismatches in the digital-mixing stage. This paper analyzes the inefficiency in deploying a classical look up table (LUT) predistortion scheme for this impairment. Then a much more effective predistortion scheme based on a run-time binary-tree descent searching scheme is proposed to tackle the problem. Simulation results show that, for both 64-QAM and 256-QAM modulation schemes, the error-vector-magnitude (EVM) can be improved from around -24 dB to less than -42 dB with a power-efficient implementation, which leaves substantial design margin for other nonidealities distorting the transmitted signal. The power consumption of the predistortion block, exploiting dynamic voltage scaling, is 5.52 mW when operating at a sampling rate of 600 Mega samples per second (MSPs) and scales to 3.25 and 1.48 mW when reducing the sample rate to 400 and 200 MSPs.

Adaptive filter based low complexity digital intensive harmonic rejection for SDR receiver

Harmonic rejection mixing is indispensable in software defined radio receivers employing switched mixers. Current analog multi-path mixing solution suffers from phase and gain mismatches along the paths and as a consequence cannot provide sufficient harmonic rejection. In this paper, we present a low complexity flexible digital intensive harmonic rejection architecture and show how it can be used to enhance the rejection of any single harmonic interference by adaptively combining the different mixing paths. Simulation results show that the proposed method can reject any single interferer adaptively by over 80 dB, which is sufficient for practical applications.

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor

Recently, various specialized Software Defined Radio (SDR) baseband processors have been proposed for meeting the high performance and programmability requirements for emerging wireless communication applications. In order to support high throughput wireless communication, the SDR baseband processors typically employ many parallel computation elements, which may also be used for performing other signal processing applications. This paper explores the feasibility of performing complex media processing on such SDR baseband processors. Specifically, the full HD 1080p state-of-the-art H.264/AVC media decoding has been implemented onto a recent version of the ADRES based SDR baseband processor. Since the processor was originally designed exclusively for wireless baseband applications, algorithm and architecture co-optimizations are required to make the goal feasible. Following algorithm analysis, the computationally dominant tasks of the H.264/AVC, including the motion compensation, the intra prediction, the inverse integer transform, and the deblocking filter, have been selected to be mapped onto the ADRES. The experimental results show that, with limited architectural extensions, the ADRES based baseband processor achieves competitive performance efficiency, even compared with several processors that are specifically optimized for the media decoding application.

On the General Mathematical Framework, Calibration/Compensation Method, and Applications of Non-Ideal Software Defined Harmonics Rejection Transceivers

Recently harmonic interference rejection has been recognized as a crucial bottleneck of truly wide-band software defined radio transceivers. Phase and gain mismatches among mixing paths, typical for nanoscale technology nodes, severely impact the achievable rejection ratio in classical harmonic rejection transceivers. This paper proposes an alternative digital intensive architecture, which enables increased harmonic interference rejection for wide-band SDR transceivers impacted by severe gain and phase mismatches. A generic mathematical framework of the target architecture is introduced to support a systematic design space exploration for multi-path harmonic interference rejection transceivers. With the framework, an iterative on-die estimation and compensation of mismatch for both the transmitter and receiver are presented. Case study with four mixing paths shows that ideal rejection can be achieved when targeting a single dominating harmonic interferer, and joint suppression of the 3rd and 5th order harmonic interferers of at least 70 dB can be obtained under realistic radio input scenarios.