Xiaowei Sun

Novel buffer engineering: A concept for fast switching and low loss operation of planar IGBT

Abstract For the first time, an insulated gate bipolar transistor with a novel buffer is proposed and verified by two-dimensional (2D) mixed device-circuit simulations. The structure of the proposed device is almost identical with that of the conventional IGBT, except for the buffer layer which is formed by employing a three-step, gradually changing doping n + structure. Compared with the conventional IGBT, the proposed device exhibits better trade-off relation between the conduction and switching losses. The turn-off time is halved from 9.4xa0μs of the conventional IGBT to 4.5xa0μs of the proposed device, so the operation speed of the proposed device is greatly improved. Further, the forward blocking voltage is enormously increased from 907xa0V of the proposed device to 1278xa0V of the proposed device, which is required for high power operation.

NEW COLLECTOR OF PLANAR INSULATED GATE BIPOLAR TRANSISTOR FOR BROAD APPLICATIONS

A new concept of Insulated Gate Bipolar Transisitor (IGBT) with a Si/Ge layer collector is proposed to meet different requirements for turn-on voltage and turn-off time. The operation principles of IGBT are discussed and the energy band diagram of Si/Ge heterojunction is employed to explain the inner dynamic mechanism of the proposed IGBT. Two-dimensional (2D) device-circuit mixed-mode simulations indicate that the tail-current, which is a major cause of the power loss and limits the operation speed of the device, is suppressed effectively by using the Si/Ge layer collector. On the other hand, turn-on voltage is increased by the use of the Si/Ge collector. Furthermore, the turn-on voltage is increasing with the increase of the areal rate of the Ge region in the whole collector, while the turn-off time is reversed. This valuable information leads to the freely tunable planar IGBT by adapting the different areal rates of the Ge region to cast to different actual situations. Detailed physical explanations ar...

A high-power solid-state p+–n–n+ diode for picosecond-range closing switching

The solid-state delayed breakdown diode (DBD) is investigated in this paper. Special attention is given to the internal dynamics and physical nature that underlie the delayed breakdown process. We investigate the source of initial carriers which trigger the front, explain the origin of the time delay in triggering the front, and detail the mechanism of front propagation. Then, a Si-based DBD with an improved three-step gradually changing doping structure is reviewed in this paper. The output voltage of an identical-sized improved DBD has been shown to increase from 2.12 kV to 2.25 kV and the dV/dt peak of the output voltage has been increased from 30 kV ns−1 to 43.87 kV ns−1 with the same driving voltage through two-dimensional device simulations. Finally, a Si/SiGe heterojunction DBD with high-speed capability for picosecond switching is presented. Switch speed of the identical-sized Si/SiGe DBD (144.9 kV ns−1) appears to be more than four times higher than that of the conventional Si device (30 kV ns−1).

Novel plugged p/sup +/ collector structure for high-performance IGBT

For the first time, a novel plugged p+ collector is proposed for the insulated gate bipolar transistor (IGBT) and evaluated in detail by using two-dimensional numerical simulations as an effective method to control the collector injection efficiency and enhance the turn-off performance. Extensive simulations indicate the turn-off time of this device is reduced and the forward blocking capability is improved significantly compared to the conventional IGBT. Most importantly, the proposed IGBT breaks the deadlock between the low on-state energy loss and fast speed by engineering the whole heavy-doped p+ collector into a high-injection-efficiency heavy-doped p + region and a low-injection-efficiency lightly doped p- region to offer a more superior on-state/switching tradeoff. The heavily doped p+ region assures an optimum level of conductivity modulation required for a reasonable on-state voltage drop in the n- drift region, while the lightly doped p- region accelerates the devices turn-off. These advantages make this device an attractive candidate for high-frequency high-power applications

Adjustable high-speed insulated gate bipolar transistor

A new adjustable insulated gate bipolar transistor (IGBT) with Si/SiGe heterojunction collector structures is proposed to improve the operation speed and decrease the turnoff power loss by suppressing the tail-current. SiGe collector provides low contact resistance without consequently sacrificing turnoff losses, and also acts to suppress hole-injection into drift region during on-state and accelerate the clear sweep of the holes when the device is cutoff. On the other hand, turn-on voltage loss is increased due to the use of SiGe collector. This drawback can be minimized by using lower percentages of Ge in SiGe, since the potential barrier height at the Si/SiGe junction is controlled by the percentage of Ge in SiGe, which means the proposed IGBT can be tuned freely to meet different needs by means of changing the percentage of Ge region in the SiGe. Further, the proposed IGBT exhibits a more superior on-state/switching tradeoff relation when compared to the conventional IGBT. Two-dimensional device and circuit mixed-mode simulations are also performed to offer valuable information about the internal dynamical mechanisms of these devices, thus improving the understanding of device performance in SiGe collector applications

A NOVEL PT AND NPT MIXED IGBT HAVING A NEW n-BUFFER LAYER

For the first time, a novel mixed insulated gate bipolar transistor (MIGBT) is proposed and verified by two-dimensional (2D) mixed device-circuit simulations. The structure of the proposed device is almost identical with that of the conventional IGBT, except for the buffer layer which is formed by employing the n+/n- structure, so that the trade-off relation between the conduction and switching losses is greatly improved and efficiently decoupled. Furthermore, the proposed device exhibits larger forward blocking voltage and positive temperature coefficient of the forward voltage drop, facilitating parallel integration.

Improved solid-state DBD for picosecond switch

We propose a Si-based delayed breakdown diode (DBD) with an improved three-step gradual changing doping structure for picosecond semiconductor closing switch and discuss the physical process, which underlies the operation principle of high-power closing switch. From the results of two-dimensional mixed device-circuit simulations and theoretical analysis, several parameters of utmost important on the optimal design of picosecond switch are discussed in detail. Performance comparisons of traditional and improved DBDs are given systematically.

Investigation and Improvement of high performance planar IGBT

In this paper, for the first time, an insulated gate bipolar transistor with an improved buffer is proposed to improve the IGBT losses. The structure of the proposed device is almost identical with that of the conventional IGBT, except for the buffer layer which is formed by employing a very highly doped stripped n+ and a weakly doped n structure. Compared with the conventional PT-IGBT, the proposed device exhibits a better trade-off relation between the conduction and switching losses. An interesting feature of the improved IGBT is that its on- resistance(on-state losses) can be largely decreased at the expenditure of a moderate and neglectable increase in turn-off time. The weakly doped n buffer region leads to a high injection efficiency anode providing an optimum level of conductivity modulation required for a given on-state voltage drop in the n- drift region, while the very highly doped n+ buffer region results in a low injection anode accelerating the device turn-off. Detailed physical mechanisms are given.

Effective target tracking from IR image sequence

A novel TBD algorithm for tracking dim moving point target in IR image sequence with low SNR was demonstrated. Original images are preprocessed using temperature non-linear elimination and Top-hat operator, and then a composite frame is obtained by projecting operation along the time axis to reduce 3D spatio-temporal scanning for target to 2D spatial hunting. Finally the target trajectory is tracked under the condition of constant false-alarm probability (CFAR). From the experimental results, the algorithm can successfully detect dim moving point target and accurately estimate its trajectory. The algorithm, insensitive to the velocity mismatch and the changes of statistical distribution of background clutter, is adaptable to real-time target detection and tracking.