Xiaoxing Zhang

Design and implementation of UWB pulse with multiple narrow-band interferences mitigation

In this paper, a novel ultra-wideband (UWB) pulse shaping method was presented to generate IR-UWB waveforms which can suppress multiple narrow-band interferences. The proposed method includes two steps. First, to completely satisfy and fully utilize the FCC power spectral density mask, an “interim-pulse” was generated by combining several Gaussian derivative pulses with proper combination coefficients. Then, combining two such “interim-pulses” with a certain delay time, a composite UWB waveform which can mitigate multiple narrowband interferences was eventually generated. To verify the accuracy of the proposed method, a simulation setup was conducted by using MATLAB. Moreover, a low-power, low-cost waveform generator was designed and simulated with Spectra-RF 0.13um CMOS technology. The results indicate that the composite waveform generated by the proposed method can suppress multiple narrow-band interferences by introducing inherent notch frequencies in the power spectral density. Furthermore, the notch frequencies and the number of notches can be adjusted by changing the delay time.

A wide range low power CMOS radio frequency ring oscillator

This paper presents a wide frequency range, low power dissipation CMOS voltage controlled ring oscillator based on three-stage differential current-steering amplifiers (CSA) cell. The frequency of oscillator has a highly linear relationship with voltage. The VCO circuit realized through 0.18µm CMOS process parameter shows wide operating frequency from 1.624GHz to 3.229 GHz. The simulation result shows that power dissipation is 1mW with 1.8V power supply voltage.

Low Power CMOS High Speed Dual-Modulus 15/16 Prescaler for Wireless Communications

This paper introduces a high speed, low power CMOS 15/16 dual-modulus prescaler (DMP) based on true single-phase-clock (TSPC) and transmission gates (TGs) cell. A glitch elimination TSPC is used in the synchronous counter. TGs are used in the critical path. The DMP circuit implemented in 0.18µm CMOS process. The simulation results are provided. It shows wide operating frequency from 0.5GHz to 3.125GHz. It comsumes 4.23mW with 1.8V power supply voltage at 3.125GHz.

Improved embedded EEPROM in 0.35μMCMOS technology with small-scale

This paper presents a low-power embedded EEPROM in a short-range passive RFID tag. This tag was designed according to ISO/IEC 15693 protocol. An improved structure of array circuit is proposed which can reduce leakage of memory bit cell efficiently. The proposed circuits can reduce maximum to 8μA per bit cell. A new RFID EEPROM timing design and its optimized control circuit are developed. The fabrication technology is the 0.35-μm four-metal two-poly mixed signal CMOS process with embedded EEPROM. The low power consumption to erase /write is 38 μA, and reading power consumption is 2.2 μA at 2.6V.

A low cost low quiescent dissipation DC-DC converter for wireless sensor networks

This paper proposes a compact DC-DC buck converter with low output power and very low quiescent current dissipation for use in an ultra-capacitor based wireless sensor networks (WSNs) nodes. This converter is controlled by a self-oscillation topology in order to achieve less silicon area and lower quiescent dissipation than the conventional designs. The work is implemented in the standard 0.35um CMOS process with a die size of 0.05mm2 and the total quiescent current is only 80uA. Simulation results show that at 1.2V output for 50mA load, the power supply regulation ratio is 1.3%. And the load regulation ratio is 1.2% within the whole load range.

A 0.18 µm low power CMOS radio frequency LC oscillator for broadband wireless communication applications

This paper presents a detailed analysis on the relationship between quality factor (Q) and the amplitude of CMOS LC VCO. It is shown that controlled voltage amplitude is benefit for acquiring a large Q of the oscillator. Low power and phase noise of LC VCO can be optimized by tuning Q of tank. The analysis has been carried out both theoretically and by simulation for the design of a low power and low phase noise LC VCO in a standard 0.18µm CMOS process. The VCO with on-chip spiral inductor is operating from 2.9 to 3.9 GHz. The simulation phase noise level is −113 dBc/Hz at 1MHz offset frequency while dissipating only 2.4mWat a 1.8V power supply.

A low-IF front-end receiver in 0.18-µm CMOS for 2.4-GHz Band IEEE802.15.4 WPAN applications

A low-IF front-end receiver suitable for the IEEE 802.15.4 standard operate at the 2.4-GHz band which was designed in 0.18-µm CMOS technology is presented. In the receiver, a single-input to differential-output LNA is used to save DC current and chip area, folded mixer architecture is used to improve noise performance. The front-end receiver has 12.24 dB of single sideband noise figure(SSBNF), −11.2 dBm of third-order input intercept point(IIP3), and 25.5 dB of voltage gain. It consumes 4.2 mA of DC current from a 1.8-V power supply.