Xiaoyan Xiang

Timing monitoring paths selection for wide voltage IC

Wide voltage range circuit has got widespread attention where in-situ timing monitoring based adaptive voltage scaling (AVS) becomes necessary to reduce the design margin. However, the severe PVT variations across near-threshold to super-threshold cause too many critical paths to be monitored. Here activation oriented monitoring paths selection method is proposed to reduce the monitored paths for wide voltage IC. The minimum delay value of the longest activated path is found by dynamic timing analysis and set as the selection threshold. Those paths longer than this threshold by STA analysis are selected to be monitored. Applied on a 40 nm AVS Systemon-Chip, it reduces the monitoring paths to only 22% of all critical paths with remarkable power gains under 0.6V–1.1V.

An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection

This brief presents an energy-efficient electrocardiogram processor for arrhythmia detection with a weak-strong hybrid classifier that includes a weak linear classifier (WLC) and a strong support vector machine (SVM) classifier. WLC can only identify the beats with distinct characteristics by performing simple threshold comparisons based on beat interval feature and a novel morphology feature named QRS area ratio. The beats that are unclassified by WLC will activate the more powerful but energy-guzzling SVM classifier. Principal component analysis (PCA) is applied for feature dimension reduction to lower the complexity of SVM classifier and a sparse matrix computing architecture is exploited to reduce the computation burden of PCA. Implemented in SMIC 40LL CMOS process, the processor has a total area of 0.12 mm2. It achieves 1.98-uW power consumption in WLC mode and 3.76-uW in SVM mode under 1.1-V voltage supply and 10-KHz operating frequency, with energy dissipation of 6.8/30.3 nJ per beat classification for the two modes, respectively. The overall accuracy for MIT-BIH arrhythmia database is 98.2% with energy reduction of 41.7% compared to a single SVM classifier.

A dual-mode ECG processor with difference-insensitive QRS detection and lossless compression

This work presents a low power dual-mode electrocardiogram (ECG) processor with QRS detection and ECG signal lossless compression. An adaptive difference-insensitive filter is proposed to eliminate redundant information in signal for QRS detection, which helps minimize calculation power. It is also adopted as a noise estimator and used to improve the noise tolerance of the detector. Furthermore, in compression mode, linear predictor with a novel adaptive length encoder is applied to the ECG data lossless compression, achieving a compression ratio (CR) of 2.42 with 1.06 K gate count. Implemented in 40nm CMOS technology, the processor has a total core area of 6806 μm2, with 36 nW power consumption in detection mode and 7.3 nW in compression mode under a supply voltage of 0.5 V.

A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction

Timing error resilience is a promising alternative to eliminate margins and improve energy efficiency in subthreshold and near-threshold processors. However, the existing techniques have some limitations, such as uncontaminated architecture registers (ARs), strict timing constraints on error consolidation and propagation, and high design complexity. To address these limitations, a new timing error resilience technique based on sacrificial instruction-level registers is proposed. It dynamically captures and incrementally records the changes of ARs at each instruction boundary. Once a timing error occurs, it only needs to restore the changed ARs to a preerror state. Then, the erroneous instruction can be safely reexecuted. This technique is applicable to different processors. The 32-bit embedded processor employing the proposed technique is demonstrated in a 40-nm CMOS technology. This variation-tolerant processor operates at 27.4 MHz under 0.6 V with 8.7% total area overhead compared with the baseline without timing error resilience. At the same throughput, the proposed technique achieves 44% and 27% energy benefits compared with the baseline and the canary technique, respectively.

Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor

Energy-efficiency optimization occupies an important position in the Internet of Things application. The error-resilience technique has begun to emerge and brought the performance and energy benefits as a new vision for alternative computing, because it eliminates the overconstrained margin in current processor design flow and protects the system from process, supply voltage, temperature, and aging variations through an error-resilient mechanism rather than expensive guardbands. However, as a traditional clock-tree power optimization technique, the clock gating mechanism cannot work in such a system when it faces the timing violation problem. In this paper, we propose an error-resilient integrated clock gate (ERICG) and its automatic integration methodology in error detection and correction (EDAC) system design flow. ERICG can provide the ability of in situ timing EDAC with only four additional transistors compared with a conventional integrated clock gate. The SPICE simulation shows that it is a metastable-hardened cell and can work well in the wide voltage operation (0.5~ 1.1 V) including the near-threshold region. We implement it in a commercial C-SKY CK802 processor based on an SMIC 40-nm technology. The result shows that it improves the energy efficiency by 68% compared with the non-EDAC design and lowers the total power by 28.72% over the conventional EDAC design at 0.6 V.

A low power QRS detection processor with adaptive scaling of processing resolution

This work presents a power efficient QRS detection processor with self-adjustable processing resolution. As reducing the resolution of electrocardiogram (ECG) data in certain degree has little effect on the detection accuracy but helps cut down the calculation power, a total of eight processing resolutions are supported in the processor, which can bring different levels of dynamic power reduction. The processing resolution is scaled adaptively based on the QRS detection result to achieve optimized energy efficiency and guarantee acceptable detection performance. The processor is implemented in SMIC 40 nm CMOS technology and has a total area of 5655 um2. When tested on MIT-BIH arrhythmia database with 50MHz operating frequency and 0.9V voltage supply, its power consumption is 77.7 uW, which is reduced by 27.4% compared to the original processor, while the area is only increased by 6.7%. And it also achieves relatively high detection result, with an average sensitivity of 98.63% and positive prediction of 98.86%.

An energy-efficient parallel VLSI architecture for SVM classification

This letter presents an energy-efficient VLSI architecture for SVM classification. Instead of accurate calculation, cost-reduced computing elements based on approximative techniques are designed to complete computation-intensive operations in the SVM-based classifier to save energy and resources. Besides, a partial parallel structure is applied to eliminate dimensional constraints for inputs of classifiers and balance between classification speed and energy consumption. We adopt 55-nm CMOS process to implement the proposed design. It occupies 0.0901mm2 area and consumes 15.9mW at operating frequency of 100MHz and from an operating voltage of 1V. Experiment shows that the design provides an area reduction by 41.5% and a significant saving in energy efficiency by 61.8% compared with the baseline model.

An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs

Among prior short paths padding algorithms, greedy heuristic based on the number of short paths had been proven to be area saving and fast. For ultra-low supply multi-voltage designs, however, delay buffers explode due to improper padding locations caused by unconsidered delay variations. To overcome this problem, we propose a new evaluation function “effectiveness” for greedy heuristic, to characterize the benefit of buffer insertion, thereby to optimize the allocation of padding delay and reduce buffer overhead. An improved algorithm to dynamically update slacks during delay assignment stage is also introduced. Experimental results show average area reduction of 91.6% compared to the prior method.

A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs

A metastability-immune error-resilient flip-flop (MIERFF) is proposed to eliminate timing margins. It detects timing errors by generating and capturing a pulse that is wide enough to avoid metastability, in response to the data input transition. Timing errors are immediately corrected by dynamically making the master latch transparent to resample the late-arriving data. The MIERFF improves the system reliability and reduces the correction performance penalty. We apply the MIERFF to a 32-bit embedded processor in a 40 nm CMOS technology. Simulation results show that the proposed design under 0.6V consumes 47% less energy than the traditional worst case design and achieves 6%–38% energy benefits over previous error detection and correction designs.

Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput

In advanced technology nodes, large timing margins must be added to allow for worse process, voltage, temperature, and aging variations. The error detection and correction (EDAC) technique effectively eliminates these margins by timing speculation, but the high design complexity and large hardware cost make many existing EDAC systems unsuitable for commercial processors. Based on the instruction-level locality of timing errors, a collaborative EDAC approach is proposed to address this issue. The hardware layer adopts simple and low cost EDAC circuits to ensure correct operation when timing error occurs, while a runtime software layer prevents recurring errors of the same instruction by sending timing error alarms to the hardware layer. Cooperation of both layers, accompanied with the proposed profile-guided timing error avoidance algorithm, eliminates more than 95% of errors with small runtime overhead. This significantly improves overall performance and alleviates pressure on the EDAC circuits. Experimental results based on the three-stage commercial CK802 processor in SMIC 40LL process present that the approach has improved the peak performance of the baseline EDAC system (Razor-Lite + half-frequency replay) by 8% and reduced the energy consumption by 25%, with less than 1.4% area overhead.