Xin Meng

A 16-bit 1KHz bandwidth micro-power multi-step incremental ADC for multi-channel sensor interface

In this paper, a micro-power three-step Incremental ADC (IDC) is presented. The proposed IDC achieves an equivalent order of six, realized by only three integrators. Compared to traditional IDCs, the proposed topology can be more power-efficient by implemented with the very low Oversampling Ratio (OSR).

Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays

This paper presents several novel low-power low-distortion ΔΣ modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTAs requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single- and double-sampled third-order ΔΣ modulators with and without noise coupling were analyzed and simulated.

A noise-coupled low-distortion delta-sigma ADC with shifted loop delays

A low-power low-distortion ΔΣ ADC topology with shifted loop delays is proposed. Compared to the conventional low-distortion modulator, this topology can relax the critical timing for quantization and DEM by shifting the loop delay from the last integrator to the feedback path. Also, by adding one more feedback path, the last integrator can achieve both integration and active summation. Noise-coupled technique can also be utilized in the proposed modulator. To verify the effectiveness of this topology, a third-order noise-coupled ΔΣ modulator is analyzed and simulated.

A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback

A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and applies reduced error signal to the loop filter, thus enhancing the loop filter linearity. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm2 and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

Power-on digital calibration method for delta-Sigma ADCs

A digital calibration method is presented for delta-sigma ADCs with focus on feedback DAC mismatch error correction. The DAC mismatch information is acquired, and then the nonlinearity is cancelled in the digital domain while the ADC operates. Unlike dynamic element matching which is commonly run between non-overlapping clock phases, the proposed method does not have the restriction and introduces no excess loop delay. The effectiveness of the proposed scheme was demonstrated with implementation of a third-order 15-level delta-sigma ADC.

A noise-coupled time-interleaved delta-sigma modulator with shifted loop delays

Noise coupling and time interleaving are effective methods for expanding the bandwidth of the low-power wideband delta-sigma modulators. In this paper, a discrete-time ΔΣ modulator topology with these two technologies, combined with shifted loop delays, is proposed. Noise coupling and time interleaving between the two channels enhance the effective order of the noise shaping function. Shifting the loop delays relaxes the critical timing for the DEM. Also, the last integrator in the loop filter performs both integration and active summation. To verify the effectiveness of this topology, a third-order noise-coupled time-interleaved ΔΣ modulator with shifted loop delays is analyzed and simulated.

A passive CMOS low-pass filter for high speed and high SNDR applications

A new passive switched-capacitor low-pass filter topology is presented. The sampling rate is high due to the reduced number of clock phases and switches connected to each capacitor. Also, this scheme decreases the filter nonlinearity. Verified by simulations, the noise analysis of the filter shows superior performance compared to active SC filters. These features, and a wide frequency tuning range, make the filter suitable for high-speed, low noise, and low power applications. A 7th-order 400 MS/s filter was designed in 0.18 μm AKM CMOS technology. Simulations verify that it can achieve over 100 dB attenuation at 200 MHz frequency, while consuming only dynamic power.

A fully-differential input amplifier with band-pass filter for biosensors

An on-chip teraohm resistance realization scheme using a switched-capacitor ladder is presented in this paper. Linear tuning of the resistance is realized by controlling the sampling frequency. Using this scheme, a band-pass filter with very low corner frequency (~ 0.3 Hz) was implemented in a fully differential amplifier for a small chip area in a standard CMOS process.

Double-sampled wideband delta-sigma ADCs with shifted loop delays

Double sampling for delta-sigma ADCs is an effective technique for wideband and low-power data conversion. This paper proposes a double-sampled delta-sigma modulator topology with shifted loop delays. Compared with existing double-sampled modulators, this architecture implements the inherent quantization delay by shifting the delay from the last integrator to the quantizer, and it relaxes critical timing for DEM by shifting the delay from the first integrator to the feedback path. Also, by inserting one more delay in the signal path, the proposed modulator keeps the low-distortion property. To verify the effectiveness of the proposed topology, a second-order double-sampled delta-sigma modulator was designed and simulated.

Bootstrapping techniques for floating switches in switched-capacitor circuits

Bootstrapping techniques improve the linearity of switched-capacitor circuits, especially for low supply voltage. This paper proposes simple but effective techniques for bootstrapping floating switches. The method is applicable to such fundamental circuits as sample-and-hold (S/H) stages, switched-capacitor (SC) filters and SC amplifiers. It can make the on-resistance and channel charge of the switches independent of the signal, and hence enables linear operation even for low bias voltages.