Gabor C. Temes

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

In linear ICs fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifiers most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Random error effects in matched MOS capacitors and current sources

Explicit formulas are derived using statistical methods for the random errors affecting capacitance and current ratios in MOS integrated circuits. They give the dependence of each error source on the physical dimensions, the standard deviations of the fabrication parameters, the bias conditions, etc. Experimental results, obtained for both matched capacitors and matched current sources using a 3.5-/spl mu/m NMOS technology, confirmed the theoretical predictions. Random effects represent the ultimate limitation on the achievable accuracy of switched-capacitor filters, D/A converters, and other MOS analog integrated circuits. The results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.

Switched-capacitor circuit design

Circuit design techniques are described for switched-capacitor filters, modulators, rectifiers, detectors, and oscillators. The applications of these circuits in telecommunications, speech processing, and other signal-processing systems are also briefly discussed.

Design-oriented estimation of thermal noise in switched-capacitor circuits

Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI ). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter.

A 20-V four-quadrant CMOS analog multiplier

A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilberts six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.

Theory and applications of incremental /spl Delta//spl Sigma/ converters

Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.

Random errors in MOS capacitors

The effects of random edge variations and deviations of oxide thickness and permittivity are examined. Making only a few basic assumptions, it is shown that edge effects introduce a relative capacitance error /spl Delta/C/C/spl alpha/C/SUP -3/4/, while the oxide variations cause /spl Delta/C/C/spl alpha/C/SUP -1/2/. Error bounds are derived for C in terms of the variances of the linear dimensions and oxide permittivity. For a capacitor C realized as a parallel connection of n unit capacitors of values C/n, the relative error caused by edge effects is n/SUP 1/4/ times larger than for a single capacitor of value C. The relative error due to oxide variations remains the same for the two realizations. All theoretical results agree with physical consideration, as well as the Monte Carlo simulations performed.

A 16-bit low-voltage CMOS A/D converter

A/D converters used in telemetry, instrumentation, and measurements require high accuracy, excellent linearity, and negligible DC offset, but need not be fast. A simple and robust instrumentation A/D converter, fabricated in a low-voltage 4-/spl mu/m CMOS technology, is described. The measured overall accuracy was 16 bits. Using a digital compensation for parasitic effects, both offset and nonlinearity were below 12 /spl mu/V. With analog compensation, the offset was 60 /spl mu/V and the nonlinearity below 15 /spl mu/V. These results indicate that even higher accuracy can be achieved using higher voltage technology.

A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements

A second-order multibit Sigma Delta (sigma-delta) analog-to-digital converter (ADC) with a 4-b internal quantizer is described. It uses a simple and fast digital correction scheme. A correlated-double-sampling (CDS) fully differential integrator was used, in which the op amp needed only a low slew rate and moderate bandwidth for a sampling rate of 5.25 MHz. A second-order modulator was fabricated in the standard MOSIS p-well 2- mu m CMOS process. The excellent measured linearity and high S/(N+D) ratio (95 dB with an oversampling ratio of only 128) of the corrected converter verified the practical advantages of the proposed architecture. >

Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection

For pt. I see ibid., vol. 47, no. 7, p. 621-8 (2000). This part describes a different adaptation strategy. It relies on the injection of a pseudorandom two-level test signal at the input of the first-stage quantizer, where it is added to the quantization noise. The test signal then leaks into the output signal, where it can be detected and used to control the digital noise-cancellation filter. This paper describes the correction process, as well as some efficient structures for implementing it, and demonstrates the effectiveness of the technique by describing three design examples.